cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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arm,smmu-v3.yaml (2824B)

      1# SPDX-License-Identifier: GPL-2.0-only
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: ARM SMMUv3 Architecture Implementation
      8
      9maintainers:
     10  - Will Deacon <will@kernel.org>
     11  - Robin Murphy <Robin.Murphy@arm.com>
     12
     13description: |+
     14  The SMMUv3 architecture is a significant departure from previous
     15  revisions, replacing the MMIO register interface with in-memory command
     16  and event queues and adding support for the ATS and PRI components of
     17  the PCIe specification.
     18
     19properties:
     20  $nodename:
     21    pattern: "^iommu@[0-9a-f]*"
     22  compatible:
     23    const: arm,smmu-v3
     24
     25  reg:
     26    maxItems: 1
     27
     28  interrupts:
     29    minItems: 1
     30    maxItems: 4
     31
     32  interrupt-names:
     33    oneOf:
     34      - const: combined
     35        description:
     36          The combined interrupt is optional, and should only be provided if the
     37          hardware supports just a single, combined interrupt line.
     38          If provided, then the combined interrupt will be used in preference to
     39          any others.
     40      - minItems: 1
     41        items:
     42          - enum:
     43              - eventq     # Event Queue not empty
     44              - gerror     # Global Error activated
     45          - const: gerror
     46          - enum:
     47              - cmdq-sync  # CMD_SYNC complete
     48              - priq       # PRI Queue not empty
     49          - enum:
     50              - cmdq-sync
     51              - priq
     52
     53  '#iommu-cells':
     54    const: 1
     55
     56  dma-coherent:
     57    description: |
     58      Present if page table walks made by the SMMU are cache coherent with the
     59      CPU.
     60
     61      NOTE: this only applies to the SMMU itself, not masters connected
     62      upstream of the SMMU.
     63
     64  msi-parent: true
     65
     66  hisilicon,broken-prefetch-cmd:
     67    type: boolean
     68    description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
     69
     70  cavium,cn9900-broken-page1-regspace:
     71    type: boolean
     72    description:
     73      Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
     74      register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
     75      doesn't support SMMU page1 register space.
     76
     77required:
     78  - compatible
     79  - reg
     80  - '#iommu-cells'
     81
     82additionalProperties: false
     83
     84examples:
     85  - |+
     86    #include <dt-bindings/interrupt-controller/arm-gic.h>
     87    #include <dt-bindings/interrupt-controller/irq.h>
     88
     89    iommu@2b400000 {
     90            compatible = "arm,smmu-v3";
     91            reg = <0x2b400000 0x20000>;
     92            interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
     93                         <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
     94                         <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
     95                         <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
     96            interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
     97            dma-coherent;
     98            #iommu-cells = <1>;
     99            msi-parent = <&its 0xff0000>;
    100    };