arm,smmu.yaml (9523B)
1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - const: qcom,smmu-v2 32 33 - description: Qcom SoCs implementing "arm,mmu-500" 34 items: 35 - enum: 36 - qcom,qcm2290-smmu-500 37 - qcom,sc7180-smmu-500 38 - qcom,sc7280-smmu-500 39 - qcom,sc8180x-smmu-500 40 - qcom,sc8280xp-smmu-500 41 - qcom,sdm845-smmu-500 42 - qcom,sdx55-smmu-500 43 - qcom,sdx65-smmu-500 44 - qcom,sm6350-smmu-500 45 - qcom,sm8150-smmu-500 46 - qcom,sm8250-smmu-500 47 - qcom,sm8350-smmu-500 48 - qcom,sm8450-smmu-500 49 - const: arm,mmu-500 50 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 51 items: 52 - enum: 53 - qcom,sc7180-smmu-v2 54 - qcom,sdm845-smmu-v2 55 - const: qcom,adreno-smmu 56 - const: qcom,smmu-v2 57 - description: Marvell SoCs implementing "arm,mmu-500" 58 items: 59 - const: marvell,ap806-smmu-500 60 - const: arm,mmu-500 61 - description: NVIDIA SoCs that require memory controller interaction 62 and may program multiple ARM MMU-500s identically with the memory 63 controller interleaving translations between multiple instances 64 for improved performance. 65 items: 66 - enum: 67 - nvidia,tegra186-smmu 68 - nvidia,tegra194-smmu 69 - nvidia,tegra234-smmu 70 - const: nvidia,smmu-500 71 - items: 72 - const: arm,mmu-500 73 - const: arm,smmu-v2 74 - items: 75 - enum: 76 - arm,mmu-400 77 - arm,mmu-401 78 - const: arm,smmu-v1 79 - enum: 80 - arm,smmu-v1 81 - arm,smmu-v2 82 - arm,mmu-400 83 - arm,mmu-401 84 - arm,mmu-500 85 - cavium,smmu-v2 86 87 reg: 88 minItems: 1 89 maxItems: 2 90 91 '#global-interrupts': 92 description: The number of global interrupts exposed by the device. 93 $ref: /schemas/types.yaml#/definitions/uint32 94 minimum: 0 95 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 96 97 '#iommu-cells': 98 enum: [ 1, 2 ] 99 description: | 100 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 101 value of 1, each IOMMU specifier represents a distinct stream ID emitted 102 by that device into the relevant SMMU. 103 104 SMMUs with stream matching support and complex masters may use a value of 105 2, where the second cell of the IOMMU specifier represents an SMR mask to 106 combine with the ID in the first cell. Care must be taken to ensure the 107 set of matched IDs does not result in conflicts. 108 109 interrupts: 110 minItems: 1 111 maxItems: 388 # 260 plus 128 contexts 112 description: | 113 Interrupt list, with the first #global-interrupts entries corresponding to 114 the global interrupts and any following entries corresponding to context 115 interrupts, specified in order of their indexing by the SMMU. 116 117 For SMMUv2 implementations, there must be exactly one interrupt per 118 context bank. In the case of a single, combined interrupt, it must be 119 listed multiple times. 120 121 dma-coherent: 122 description: | 123 Present if page table walks made by the SMMU are cache coherent with the 124 CPU. 125 126 NOTE: this only applies to the SMMU itself, not masters connected 127 upstream of the SMMU. 128 129 calxeda,smmu-secure-config-access: 130 type: boolean 131 description: 132 Enable proper handling of buggy implementations that always use secure 133 access to SMMU configuration registers. In this case non-secure aliases of 134 secure registers have to be used during SMMU configuration. 135 136 stream-match-mask: 137 $ref: /schemas/types.yaml#/definitions/uint32 138 description: | 139 For SMMUs supporting stream matching and using #iommu-cells = <1>, 140 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 141 be programmed into the SMRn.MASK field of every stream match register 142 used). For cases where it is desirable to ignore some portion of every 143 Stream ID (e.g. for certain MMU-500 configurations given globally unique 144 input IDs). This property is not valid for SMMUs using stream indexing, or 145 using stream matching with #iommu-cells = <2>, and may be ignored if 146 present in such cases. 147 148 clock-names: 149 items: 150 - const: bus 151 - const: iface 152 153 clocks: 154 items: 155 - description: bus clock required for downstream bus access and for the 156 smmu ptw 157 - description: interface clock required to access smmu's registers 158 through the TCU's programming interface. 159 160 power-domains: 161 maxItems: 1 162 163 nvidia,memory-controller: 164 description: | 165 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 166 The memory controller needs to be programmed with a mapping of memory 167 client IDs to ARM SMMU stream IDs. 168 169 If this property is absent, the mapping programmed by early firmware 170 will be used and it is not guaranteed that IOMMU translations will be 171 enabled for any given device. 172 $ref: /schemas/types.yaml#/definitions/phandle 173 174required: 175 - compatible 176 - reg 177 - '#global-interrupts' 178 - '#iommu-cells' 179 - interrupts 180 181additionalProperties: false 182 183allOf: 184 - if: 185 properties: 186 compatible: 187 contains: 188 enum: 189 - nvidia,tegra186-smmu 190 - nvidia,tegra194-smmu 191 - nvidia,tegra234-smmu 192 then: 193 properties: 194 reg: 195 minItems: 1 196 maxItems: 2 197 198 # The reference to the memory controller is required to ensure that the 199 # memory client to stream ID mapping can be done synchronously with the 200 # IOMMU attachment. 201 required: 202 - nvidia,memory-controller 203 else: 204 properties: 205 reg: 206 maxItems: 1 207 208examples: 209 - |+ 210 /* SMMU with stream matching or stream indexing */ 211 smmu1: iommu@ba5e0000 { 212 compatible = "arm,smmu-v1"; 213 reg = <0xba5e0000 0x10000>; 214 #global-interrupts = <2>; 215 interrupts = <0 32 4>, 216 <0 33 4>, 217 <0 34 4>, /* This is the first context interrupt */ 218 <0 35 4>, 219 <0 36 4>, 220 <0 37 4>; 221 #iommu-cells = <1>; 222 }; 223 224 /* device with two stream IDs, 0 and 7 */ 225 master1 { 226 iommus = <&smmu1 0>, 227 <&smmu1 7>; 228 }; 229 230 231 /* SMMU with stream matching */ 232 smmu2: iommu@ba5f0000 { 233 compatible = "arm,smmu-v1"; 234 reg = <0xba5f0000 0x10000>; 235 #global-interrupts = <2>; 236 interrupts = <0 38 4>, 237 <0 39 4>, 238 <0 40 4>, /* This is the first context interrupt */ 239 <0 41 4>, 240 <0 42 4>, 241 <0 43 4>; 242 #iommu-cells = <2>; 243 }; 244 245 /* device with stream IDs 0 and 7 */ 246 master2 { 247 iommus = <&smmu2 0 0>, 248 <&smmu2 7 0>; 249 }; 250 251 /* device with stream IDs 1, 17, 33 and 49 */ 252 master3 { 253 iommus = <&smmu2 1 0x30>; 254 }; 255 256 257 /* ARM MMU-500 with 10-bit stream ID input configuration */ 258 smmu3: iommu@ba600000 { 259 compatible = "arm,mmu-500", "arm,smmu-v2"; 260 reg = <0xba600000 0x10000>; 261 #global-interrupts = <2>; 262 interrupts = <0 44 4>, 263 <0 45 4>, 264 <0 46 4>, /* This is the first context interrupt */ 265 <0 47 4>, 266 <0 48 4>, 267 <0 49 4>; 268 #iommu-cells = <1>; 269 /* always ignore appended 5-bit TBU number */ 270 stream-match-mask = <0x7c00>; 271 }; 272 273 bus { 274 /* bus whose child devices emit one unique 10-bit stream 275 ID each, but may master through multiple SMMU TBUs */ 276 iommu-map = <0 &smmu3 0 0x400>; 277 278 279 }; 280 281 - |+ 282 /* Qcom's arm,smmu-v2 implementation */ 283 #include <dt-bindings/interrupt-controller/arm-gic.h> 284 #include <dt-bindings/interrupt-controller/irq.h> 285 smmu4: iommu@d00000 { 286 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 287 reg = <0xd00000 0x10000>; 288 289 #global-interrupts = <1>; 290 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 293 #iommu-cells = <1>; 294 power-domains = <&mmcc 0>; 295 296 clocks = <&mmcc 123>, 297 <&mmcc 124>; 298 clock-names = "bus", "iface"; 299 };