cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

samsung,sysmmu.yaml (2893B)


      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
      8
      9maintainers:
     10  - Marek Szyprowski <m.szyprowski@samsung.com>
     11
     12description: |+
     13  Samsung's Exynos architecture contains System MMUs that enables scattered
     14  physical memory chunks visible as a contiguous region to DMA-capable peripheral
     15  devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
     16
     17  System MMU is an IOMMU and supports identical translation table format to
     18  ARMv7 translation tables with minimum set of page properties including access
     19  permissions, shareability and security protection. In addition, System MMU has
     20  another capabilities like L2 TLB or block-fetch buffers to minimize translation
     21  latency.
     22
     23  System MMUs are in many to one relation with peripheral devices, i.e. single
     24  peripheral device might have multiple System MMUs (usually one for each bus
     25  master), but one System MMU can handle transactions from only one peripheral
     26  device. The relation between a System MMU and the peripheral device needs to be
     27  defined in device node of the peripheral device.
     28
     29  MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
     30  MMUs.
     31  * MFC has one System MMU on its left and right bus.
     32  * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
     33    for window 1, 2 and 3.
     34  * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
     35    the other System MMU on the write channel.
     36
     37  For information on assigning System MMU controller to its peripheral devices,
     38  see generic IOMMU bindings.
     39
     40properties:
     41  compatible:
     42    const: samsung,exynos-sysmmu
     43
     44  reg:
     45    maxItems: 1
     46
     47  interrupts:
     48    maxItems: 1
     49
     50  clocks:
     51    minItems: 1
     52    maxItems: 2
     53
     54  clock-names:
     55    oneOf:
     56      - items:
     57          - const: sysmmu
     58      - items:
     59          - const: sysmmu
     60          - const: master
     61      - items:
     62          - const: aclk
     63          - const: pclk
     64
     65  "#iommu-cells":
     66    const: 0
     67
     68  power-domains:
     69    description: |
     70      Required if the System MMU is needed to gate its power.
     71      Please refer to the following document:
     72      Documentation/devicetree/bindings/power/pd-samsung.yaml
     73    maxItems: 1
     74
     75required:
     76  - compatible
     77  - reg
     78  - interrupts
     79  - clocks
     80  - clock-names
     81  - "#iommu-cells"
     82
     83additionalProperties: false
     84
     85examples:
     86  - |
     87    #include <dt-bindings/clock/exynos5250.h>
     88
     89    sysmmu_gsc0: iommu@13e80000 {
     90      compatible = "samsung,exynos-sysmmu";
     91      reg = <0x13E80000 0x1000>;
     92      interrupt-parent = <&combiner>;
     93      interrupts = <2 0>;
     94      clock-names = "sysmmu", "master";
     95      clocks = <&clock CLK_SMMU_GSCL0>,
     96               <&clock CLK_GSCL0>;
     97      power-domains = <&pd_gsc>;
     98      #iommu-cells = <0>;
     99    };