cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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arm,mhu.yaml (4860B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: ARM MHU Mailbox Controller
      8
      9maintainers:
     10  - Jassi Brar <jaswinder.singh@linaro.org>
     11
     12description: |
     13  The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
     14  independent channels/links to communicate with remote processor(s).  MHU links
     15  are hardwired on a platform. A link raises interrupt for any received data.
     16  However, there is no specified way of knowing if the sent data has been read
     17  by the remote. This driver assumes the sender polls STAT register and the
     18  remote clears it after having read the data.  The last channel is specified to
     19  be a 'Secure' resource, hence can't be used by Linux running NS.
     20
     21  The MHU hardware also allows operations in doorbell mode. The MHU drives the
     22  interrupt signal using a 32-bit register, with all 32-bits logically ORed
     23  together. It provides a set of registers to enable software to set, clear and
     24  check the status of each of the bits of this register independently. The use
     25  of 32 bits per interrupt line enables software to provide more information
     26  about the source of the interrupt. For example, each bit of the register can
     27  be associated with a type of event that can contribute to raising the
     28  interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
     29  processor.
     30
     31# We need a select here so we don't match all nodes with 'arm,primecell'
     32select:
     33  properties:
     34    compatible:
     35      contains:
     36        enum:
     37          - arm,mhu
     38          - arm,mhu-doorbell
     39  required:
     40    - compatible
     41
     42properties:
     43  compatible:
     44    oneOf:
     45      - description: Data transfer mode
     46        items:
     47          - const: arm,mhu
     48          - const: arm,primecell
     49
     50      - description: Doorbell mode
     51        items:
     52          - const: arm,mhu-doorbell
     53          - const: arm,primecell
     54
     55
     56  reg:
     57    maxItems: 1
     58
     59  interrupts:
     60    items:
     61      - description: low-priority non-secure
     62      - description: high-priority non-secure
     63      - description: Secure
     64
     65  clocks:
     66    maxItems: 1
     67
     68  clock-names:
     69    items:
     70      - const: apb_pclk
     71
     72  '#mbox-cells':
     73    description: |
     74      Set to 1 in data transfer mode and represents index of the channel.
     75      Set to 2 in doorbell mode and represents index of the channel and doorbell
     76      number.
     77    enum: [ 1, 2 ]
     78
     79required:
     80  - compatible
     81  - reg
     82  - interrupts
     83  - '#mbox-cells'
     84
     85additionalProperties: false
     86
     87examples:
     88  # Data transfer mode.
     89  - |
     90    soc {
     91        #address-cells = <2>;
     92        #size-cells = <2>;
     93
     94        mhuA: mailbox@2b1f0000 {
     95            #mbox-cells = <1>;
     96            compatible = "arm,mhu", "arm,primecell";
     97            reg = <0 0x2b1f0000 0 0x1000>;
     98            interrupts = <0 36 4>, /* LP-NonSecure */
     99                         <0 35 4>, /* HP-NonSecure */
    100                         <0 37 4>; /* Secure */
    101            clocks = <&clock 0 2 1>;
    102            clock-names = "apb_pclk";
    103        };
    104    };
    105
    106    firmware {
    107        scpi {
    108            compatible = "arm,scpi";
    109            mboxes = <&mhuA 1>; /* HP-NonSecure */
    110            shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
    111
    112            scpi_devpd: power-controller {
    113                compatible = "arm,scpi-power-domains";
    114                num-domains = <2>;
    115                #power-domain-cells = <1>;
    116            };
    117        };
    118    };
    119
    120  # Doorbell mode.
    121  - |
    122    soc {
    123        #address-cells = <2>;
    124        #size-cells = <2>;
    125
    126        mhuB: mailbox@2b2f0000 {
    127            #mbox-cells = <2>;
    128            compatible = "arm,mhu-doorbell", "arm,primecell";
    129            reg = <0 0x2b2f0000 0 0x1000>;
    130            interrupts = <0 36 4>, /* LP-NonSecure */
    131                         <0 35 4>, /* HP-NonSecure */
    132                         <0 37 4>; /* Secure */
    133            clocks = <&clock 0 2 1>;
    134            clock-names = "apb_pclk";
    135        };
    136    };
    137
    138    firmware {
    139        scmi {
    140            compatible = "arm,scmi";
    141            mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */
    142                     <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */
    143            mbox-names = "tx", "rx";
    144            shmem = <&cpu_scp_lpri0>,
    145                    <&cpu_scp_lpri1>;
    146
    147            #address-cells = <1>;
    148            #size-cells = <0>;
    149
    150            scmi_devpd: protocol@11 {
    151                reg = <0x11>;
    152                #power-domain-cells = <1>;
    153            };
    154
    155            scmi_dvfs: protocol@13 {
    156                reg = <0x13>;
    157                #clock-cells = <1>;
    158
    159                mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */
    160                         <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */
    161                mbox-names = "tx", "rx";
    162                shmem = <&cpu_scp_hpri0>,
    163                        <&cpu_scp_hpri1>;
    164            };
    165        };
    166    };
    167
    168...