cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,mu.yaml (3392B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NXP i.MX Messaging Unit (MU)
      8
      9maintainers:
     10  - Dong Aisheng <aisheng.dong@nxp.com>
     11
     12description: |
     13  The Messaging Unit module enables two processors within the SoC to
     14  communicate and coordinate by passing messages (e.g. data, status
     15  and control) through the MU interface. The MU also provides the ability
     16  for one processor to signal the other processor using interrupts.
     17
     18  Because the MU manages the messaging between processors, the MU uses
     19  different clocks (from each side of the different peripheral buses).
     20  Therefore, the MU must synchronize the accesses from one side to the
     21  other. The MU accomplishes synchronization using two sets of matching
     22  registers (Processor A-facing, Processor B-facing).
     23
     24properties:
     25  compatible:
     26    oneOf:
     27      - const: fsl,imx6sx-mu
     28      - const: fsl,imx7ulp-mu
     29      - const: fsl,imx8ulp-mu
     30      - const: fsl,imx8-mu-scu
     31      - const: fsl,imx8-mu-seco
     32      - const: fsl,imx93-mu-s4
     33      - const: fsl,imx8ulp-mu-s4
     34      - items:
     35          - const: fsl,imx93-mu
     36          - const: fsl,imx8ulp-mu
     37      - items:
     38          - enum:
     39              - fsl,imx7s-mu
     40              - fsl,imx8mq-mu
     41              - fsl,imx8mm-mu
     42              - fsl,imx8mn-mu
     43              - fsl,imx8mp-mu
     44              - fsl,imx8qm-mu
     45              - fsl,imx8qxp-mu
     46          - const: fsl,imx6sx-mu
     47      - description: To communicate with i.MX8 SCU with fast IPC
     48        items:
     49          - const: fsl,imx8-mu-scu
     50          - enum:
     51              - fsl,imx8qm-mu
     52              - fsl,imx8qxp-mu
     53          - const: fsl,imx6sx-mu
     54
     55  reg:
     56    maxItems: 1
     57
     58  interrupts:
     59    minItems: 1
     60    maxItems: 2
     61
     62  interrupt-names:
     63    minItems: 1
     64    items:
     65      - const: tx
     66      - const: rx
     67
     68  "#mbox-cells":
     69    description: |
     70      <&phandle type channel>
     71      phandle   : Label name of controller
     72      type      : Channel type
     73      channel   : Channel number
     74
     75      This MU support 4 type of unidirectional channels, each type
     76      has 4 channels. A total of 16 channels. Following types are
     77      supported:
     78      0 - TX channel with 32bit transmit register and IRQ transmit
     79          acknowledgment support.
     80      1 - RX channel with 32bit receive register and IRQ support
     81      2 - TX doorbell channel. Without own register and no ACK support.
     82      3 - RX doorbell channel.
     83    const: 2
     84
     85  clocks:
     86    maxItems: 1
     87
     88  fsl,mu-side-b:
     89    description: boolean, if present, means it is for side B MU.
     90    type: boolean
     91
     92  power-domains:
     93    maxItems: 1
     94
     95required:
     96  - compatible
     97  - reg
     98  - interrupts
     99  - "#mbox-cells"
    100
    101allOf:
    102  - if:
    103      properties:
    104        compatible:
    105          enum:
    106            - fsl,imx93-mu-s4
    107    then:
    108      properties:
    109        interrupt-names:
    110          minItems: 2
    111        interrupts:
    112          minItems: 2
    113
    114    else:
    115      properties:
    116        interrupts:
    117          maxItems: 1
    118      not:
    119        required:
    120          - interrupt-names
    121
    122additionalProperties: false
    123
    124examples:
    125  - |
    126    #include <dt-bindings/interrupt-controller/arm-gic.h>
    127
    128    mailbox@5d1b0000 {
    129        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    130        reg = <0x5d1b0000 0x10000>;
    131        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
    132        #mbox-cells = <2>;
    133    };