cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hisilicon,hi3660-mailbox.txt (1417B)


      1Hisilicon Hi3660 Mailbox Controller
      2
      3Hisilicon Hi3660 mailbox controller supports up to 32 channels.  Messages
      4are passed between processors, including application & communication
      5processors, MCU, HIFI, etc.  Each channel is unidirectional and accessed
      6by using MMIO registers; it supports maximum to 8 words message.
      7
      8Controller
      9----------
     10
     11Required properties:
     12- compatible:		: Shall be "hisilicon,hi3660-mbox"
     13- reg:			: Offset and length of the device's register set
     14- #mbox-cells:		: Must be 3
     15			  <&phandle channel dst_irq ack_irq>
     16			    phandle	: Label name of controller
     17			    channel	: Channel number
     18			    dst_irq	: Remote interrupt vector
     19			    ack_irq	: Local interrupt vector
     20
     21- interrupts:		: Contains the two IRQ lines for mailbox.
     22
     23Example:
     24
     25mailbox: mailbox@e896b000 {
     26	compatible = "hisilicon,hi3660-mbox";
     27	reg = <0x0 0xe896b000 0x0 0x1000>;
     28	interrupts = <0x0 0xc0 0x4>,
     29		     <0x0 0xc1 0x4>;
     30	#mbox-cells = <3>;
     31};
     32
     33Client
     34------
     35
     36Required properties:
     37- compatible		: See the client docs
     38- mboxes		: Standard property to specify a Mailbox (See ./mailbox.txt)
     39			  Cells must match 'mbox-cells' (See Controller docs above)
     40
     41Optional properties
     42- mbox-names		: Name given to channels seen in the 'mboxes' property.
     43
     44Example:
     45
     46stub_clock: stub_clock@e896b500 {
     47	compatible = "hisilicon,hi3660-stub-clk";
     48	reg = <0x0 0xe896b500 0x0 0x0100>;
     49	#clock-cells = <1>;
     50	mboxes = <&mailbox 13 3 0>;
     51};