cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sti-mailbox.txt (1374B)


      1ST Microelectronics Mailbox Driver
      2
      3Each ST Mailbox IP currently consists of 4 instances of 32 channels.  Messages
      4are passed between Application and Remote processors using shared memory.
      5
      6Controller
      7----------
      8
      9Required properties:
     10- compatible		: Should be "st,stih407-mailbox"
     11- reg			: Offset and length of the device's register set
     12- mbox-name		: Name of the mailbox
     13- #mbox-cells:		: Must be 2
     14			  <&phandle instance channel direction>
     15			    phandle   : Label name of controller
     16			    instance  : Instance number
     17			    channel   : Channel number
     18
     19Optional properties
     20- interrupts		: Contains the IRQ line for a Rx mailbox
     21
     22Example:
     23
     24mailbox0: mailbox@0  {
     25	compatible	= "st,stih407-mailbox";
     26	reg		= <0x08f00000 0x1000>;
     27	interrupts	= <GIC_SPI 1 IRQ_TYPE_NONE>;
     28	#mbox-cells	= <2>;
     29	mbox-name	= "a9";
     30};
     31
     32Client
     33------
     34
     35Required properties:
     36- compatible		: Many (See the client docs)
     37- reg			: Shared (between Application and Remote) memory address
     38- mboxes		: Standard property to specify a Mailbox (See ./mailbox.txt)
     39			  Cells must match 'mbox-cells' (See Controller docs above)
     40
     41Optional properties
     42- mbox-names		: Name given to channels seen in the 'mboxes' property.
     43
     44Example:
     45
     46mailbox_test {
     47	compatible	= "mailbox-test";
     48	reg		= <0x[shared_memory_address], [shared_memory_size]>;
     49	mboxes		= <&mailbox2 0 1>, <&mailbox0 2 1>;
     50	mbox-names	= "tx",	"rx";
     51};