cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl-pxp.txt (895B)


      1Freescale Pixel Pipeline
      2========================
      3
      4The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
      5that supports scaling, colorspace conversion, alpha blending, rotation, and
      6pixel conversion via lookup table. Different versions are present on various
      7i.MX SoCs from i.MX23 to i.MX7.
      8
      9Required properties:
     10- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
     11  imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
     12- reg: the register base and size for the device registers
     13- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
     14- clock-names: should be "axi"
     15- clocks: the PXP AXI clock
     16
     17Example:
     18
     19pxp@21cc000 {
     20	compatible = "fsl,imx6ull-pxp";
     21	reg = <0x021cc000 0x4000>;
     22	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
     23		     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
     24	clock-names = "axi";
     25	clocks = <&clks IMX6UL_CLK_PXP>;
     26};