cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,st-mipid02.txt (2709B)

      1STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
      2
      3MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
      4time. Active port input stream will be de-serialized and its content outputted
      5through PARALLEL output port.
      6CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
      7input port is a single lane 800Mbps. Both ports support clock and data lane
      8polarity swap. First port also supports data lane swap.
      9PARALLEL output port has a maximum width of 12 bits.
     10Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
     11YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
     12
     13Required Properties:
     14- compatible: shall be "st,st-mipid02"
     15- clocks: reference to the xclk input clock.
     16- clock-names: shall be "xclk".
     17- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
     18- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
     19
     20Optional Properties:
     21- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
     22	       This is an active low signal to the mipid02.
     23
     24Required subnodes:
     25  - ports: A ports node with one port child node per device input and output
     26	   port, in accordance with the video interface bindings defined in
     27	   Documentation/devicetree/bindings/media/video-interfaces.txt. The
     28	   port nodes are numbered as follows:
     29
     30	   Port Description
     31	   -----------------------------
     32	   0    CSI-2 first input port
     33	   1    CSI-2 second input port
     34	   2    PARALLEL output
     35
     36Endpoint node required property for CSI-2 connection is:
     37- data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
     38<1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
     39Endpoint node optional property for CSI-2 connection is:
     40- lane-polarities: any lane can be inverted or not.
     41
     42Endpoint node required property for PARALLEL connection is:
     43- bus-width: shall be set to <6>, <7>, <8>, <10> or <12>.
     44Endpoint node optional properties for PARALLEL connection are:
     45- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
     46LOW being the default.
     47- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
     48LOW being the default.
     49
     50Example:
     51
     52mipid02: csi2rx@14 {
     53	compatible = "st,st-mipid02";
     54	reg = <0x14>;
     55	status = "okay";
     56	clocks = <&clk_ext_camera_12>;
     57	clock-names = "xclk";
     58	VDDE-supply = <&vdd>;
     59	VDDIN-supply = <&vdd>;
     60	ports {
     61		#address-cells = <1>;
     62		#size-cells = <0>;
     63		port@0 {
     64			reg = <0>;
     65
     66			ep0: endpoint {
     67				data-lanes = <1 2>;
     68				remote-endpoint = <&mipi_csi2_in>;
     69			};
     70		};
     71		port@2 {
     72			reg = <2>;
     73
     74			ep2: endpoint {
     75				bus-width = <8>;
     76				hsync-active = <0>;
     77				vsync-active = <0>;
     78				remote-endpoint = <&parallel_out>;
     79			};
     80		};
     81	};
     82};