cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx.txt (1933B)


      1Freescale i.MX Media Video Device
      2=================================
      3
      4Video Media Controller node
      5---------------------------
      6
      7This is the media controller node for video capture support. It is a
      8virtual device that lists the camera serial interface nodes that the
      9media device will control.
     10
     11Required properties:
     12- compatible : "fsl,imx-capture-subsystem";
     13- ports      : Should contain a list of phandles pointing to camera
     14		sensor interface ports of IPU devices
     15
     16example:
     17
     18capture-subsystem {
     19	compatible = "fsl,imx-capture-subsystem";
     20	ports = <&ipu1_csi0>, <&ipu1_csi1>;
     21};
     22
     23
     24mipi_csi2 node
     25--------------
     26
     27This is the device node for the MIPI CSI-2 Receiver core in the i.MX
     28SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
     29combined with a D-PHY core mixed into the same register block. In
     30addition this device consists of an i.MX-specific "CSI2IPU gasket"
     31glue logic, also controlled from the same register block. The CSI2IPU
     32gasket demultiplexes the four virtual channel streams from the host
     33controller's 32-bit output image bus onto four 16-bit parallel busses
     34to the i.MX IPU CSIs.
     35
     36Required properties:
     37- compatible	: "fsl,imx6-mipi-csi2";
     38- reg           : physical base address and length of the register set;
     39- clocks	: the MIPI CSI-2 receiver requires three clocks: hsi_tx
     40		  (the D-PHY clock), video_27m (D-PHY PLL reference
     41		  clock), and eim_podf;
     42- clock-names	: must contain "dphy", "ref", "pix";
     43- port@*        : five port nodes must exist, containing endpoints
     44		  connecting to the source and sink devices according to
     45		  of_graph bindings. The first port is an input port,
     46		  connecting with a MIPI CSI-2 source, and ports 1
     47		  through 4 are output ports connecting with parallel
     48		  bus sink endpoint nodes and correspond to the four
     49		  MIPI CSI-2 virtual channel outputs.
     50
     51Optional properties:
     52- interrupts	: must contain two level-triggered interrupts,
     53		  in order: 100 and 101;