cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mediatek-jpeg-encoder.yaml (1751B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: MediaTek JPEG Encoder Device Tree Bindings
      8
      9maintainers:
     10  - Xia Jiang <xia.jiang@mediatek.com>
     11
     12description: |-
     13  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
     14
     15properties:
     16  compatible:
     17    items:
     18      - enum:
     19          - mediatek,mt2701-jpgenc
     20          - mediatek,mt8183-jpgenc
     21      - const: mediatek,mtk-jpgenc
     22  reg:
     23    maxItems: 1
     24
     25  interrupts:
     26    maxItems: 1
     27
     28  clocks:
     29    maxItems: 1
     30
     31  clock-names:
     32    items:
     33      - const: jpgenc
     34
     35  power-domains:
     36    maxItems: 1
     37
     38  iommus:
     39    maxItems: 2
     40    description: |
     41      Points to the respective IOMMU block with master port as argument, see
     42      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
     43      Ports are according to the HW.
     44
     45required:
     46  - compatible
     47  - reg
     48  - interrupts
     49  - clocks
     50  - clock-names
     51  - power-domains
     52  - iommus
     53
     54additionalProperties: false
     55
     56examples:
     57  - |
     58    #include <dt-bindings/clock/mt2701-clk.h>
     59    #include <dt-bindings/interrupt-controller/arm-gic.h>
     60    #include <dt-bindings/memory/mt2701-larb-port.h>
     61    #include <dt-bindings/power/mt2701-power.h>
     62    jpegenc: jpegenc@1500a000 {
     63      compatible = "mediatek,mt2701-jpgenc",
     64                   "mediatek,mtk-jpgenc";
     65      reg = <0x1500a000 0x1000>;
     66      interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
     67      clocks =  <&imgsys CLK_IMG_VENC>;
     68      clock-names = "jpgenc";
     69      power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
     70      iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
     71               <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
     72    };