cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nxp,imx-mipi-csi2.yaml (5435B)


      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
      8
      9maintainers:
     10  - Rui Miguel Silva <rmfrfs@gmail.com>
     11  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
     12
     13description: |-
     14  The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
     15  receiver IP core named CSIS. The IP core originates from Samsung, and may be
     16  compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
     17  3.3, and i.MX8 SoCs use CSIS version 3.6.3.
     18
     19  While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
     20  completely wrapped by the CSIS and doesn't expose a control interface of its
     21  own. This binding thus covers both IP cores.
     22
     23properties:
     24  compatible:
     25    enum:
     26      - fsl,imx7-mipi-csi2
     27      - fsl,imx8mm-mipi-csi2
     28
     29  reg:
     30    maxItems: 1
     31
     32  interrupts:
     33    maxItems: 1
     34
     35  clocks:
     36    minItems: 3
     37    items:
     38      - description: The peripheral clock (a.k.a. APB clock)
     39      - description: The external clock (optionally used as the pixel clock)
     40      - description: The MIPI D-PHY clock
     41      - description: The AXI clock
     42
     43  clock-names:
     44    minItems: 3
     45    items:
     46      - const: pclk
     47      - const: wrap
     48      - const: phy
     49      - const: axi
     50
     51  power-domains:
     52    maxItems: 1
     53
     54  phy-supply:
     55    description: The MIPI D-PHY digital power supply
     56
     57  resets:
     58    items:
     59      - description: MIPI D-PHY slave reset
     60
     61  clock-frequency:
     62    description: The desired external clock ("wrap") frequency, in Hz
     63    default: 166000000
     64
     65  ports:
     66    $ref: /schemas/graph.yaml#/properties/ports
     67
     68    properties:
     69      port@0:
     70        $ref: /schemas/graph.yaml#/$defs/port-base
     71        unevaluatedProperties: false
     72        description:
     73          Input port node, single endpoint describing the CSI-2 transmitter.
     74
     75        properties:
     76          endpoint:
     77            $ref: video-interfaces.yaml#
     78            unevaluatedProperties: false
     79
     80            properties:
     81              data-lanes:
     82                description:
     83                  Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
     84                minItems: 1
     85                items:
     86                  - const: 1
     87                  - const: 2
     88                  - const: 3
     89                  - const: 4
     90
     91            required:
     92              - data-lanes
     93
     94      port@1:
     95        $ref: /schemas/graph.yaml#/properties/port
     96        description:
     97          Output port node
     98
     99required:
    100  - compatible
    101  - reg
    102  - interrupts
    103  - clocks
    104  - clock-names
    105  - power-domains
    106  - ports
    107
    108additionalProperties: false
    109
    110allOf:
    111  - if:
    112      properties:
    113        compatible:
    114          contains:
    115            const: fsl,imx7-mipi-csi2
    116    then:
    117      required:
    118        - phy-supply
    119        - resets
    120    else:
    121      properties:
    122        clocks:
    123          minItems: 4
    124        clock-names:
    125          minItems: 4
    126        phy-supply: false
    127        resets: false
    128
    129examples:
    130  - |
    131    #include <dt-bindings/clock/imx7d-clock.h>
    132    #include <dt-bindings/interrupt-controller/arm-gic.h>
    133    #include <dt-bindings/interrupt-controller/irq.h>
    134    #include <dt-bindings/reset/imx7-reset.h>
    135
    136    mipi-csi@30750000 {
    137        compatible = "fsl,imx7-mipi-csi2";
    138        reg = <0x30750000 0x10000>;
    139        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
    140
    141        clocks = <&clks IMX7D_IPG_ROOT_CLK>,
    142                 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
    143                 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
    144        clock-names = "pclk", "wrap", "phy";
    145        clock-frequency = <166000000>;
    146
    147        power-domains = <&pgc_mipi_phy>;
    148        phy-supply = <&reg_1p0d>;
    149        resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
    150
    151        ports {
    152            #address-cells = <1>;
    153            #size-cells = <0>;
    154
    155            port@0 {
    156                reg = <0>;
    157
    158                mipi_from_sensor: endpoint {
    159                    remote-endpoint = <&ov2680_to_mipi>;
    160                    data-lanes = <1>;
    161                };
    162            };
    163
    164            port@1 {
    165                reg = <1>;
    166
    167                mipi_vc0_to_csi_mux: endpoint {
    168                    remote-endpoint = <&csi_mux_from_mipi_vc0>;
    169                };
    170            };
    171        };
    172    };
    173
    174  - |
    175    #include <dt-bindings/clock/imx8mm-clock.h>
    176    #include <dt-bindings/interrupt-controller/arm-gic.h>
    177    #include <dt-bindings/interrupt-controller/irq.h>
    178
    179    mipi-csi@32e30000 {
    180        compatible = "fsl,imx8mm-mipi-csi2";
    181        reg = <0x32e30000 0x1000>;
    182        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
    183        clock-frequency = <333000000>;
    184        clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
    185                 <&clk IMX8MM_CLK_CSI1_ROOT>,
    186                 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
    187                 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
    188        clock-names = "pclk", "wrap", "phy", "axi";
    189        power-domains = <&mipi_pd>;
    190
    191        ports {
    192            #address-cells = <1>;
    193            #size-cells = <0>;
    194
    195            port@0 {
    196                reg = <0>;
    197
    198                imx8mm_mipi_csi_in: endpoint {
    199                    remote-endpoint = <&imx477_out>;
    200                    data-lanes = <1 2 3 4>;
    201                };
    202            };
    203
    204            port@1 {
    205                reg = <1>;
    206
    207                imx8mm_mipi_csi_out: endpoint {
    208                    remote-endpoint = <&csi_in>;
    209                };
    210            };
    211        };
    212    };
    213
    214...