cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,stm32-dcmi.yaml (2353B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/media/st,stm32-dcmi.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) binding
      8
      9maintainers:
     10  - Hugues Fruchet <hugues.fruchet@foss.st.com>
     11
     12properties:
     13  compatible:
     14    const: st,stm32-dcmi
     15
     16  reg:
     17    maxItems: 1
     18
     19  interrupts:
     20    maxItems: 1
     21
     22  clocks:
     23    maxItems: 1
     24
     25  clock-names:
     26    items:
     27      - const: mclk
     28
     29  dmas:
     30    maxItems: 1
     31
     32  dma-names:
     33    items:
     34      - const: tx
     35
     36  resets:
     37    maxItems: 1
     38
     39  port:
     40    $ref: /schemas/graph.yaml#/$defs/port-base
     41    unevaluatedProperties: false
     42    description:
     43      DCMI supports a single port node with parallel bus.
     44
     45    properties:
     46      endpoint:
     47        $ref: video-interfaces.yaml#
     48        unevaluatedProperties: false
     49
     50        properties:
     51          bus-type:
     52            enum: [5, 6]
     53            default: 5
     54
     55          bus-width:
     56            enum: [8, 10, 12, 14]
     57            default: 8
     58
     59        allOf:
     60          - if:
     61              properties:
     62                bus-type:
     63                  const: 6
     64
     65            then:
     66              properties:
     67                hsync-active: false
     68                vsync-active: false
     69                bus-width:
     70                  enum: [8]
     71
     72        required:
     73          - bus-type
     74          - pclk-sample
     75
     76required:
     77  - compatible
     78  - reg
     79  - interrupts
     80  - clocks
     81  - clock-names
     82  - resets
     83  - dmas
     84  - dma-names
     85  - port
     86
     87additionalProperties: false
     88
     89examples:
     90  - |
     91    #include <dt-bindings/interrupt-controller/arm-gic.h>
     92    #include <dt-bindings/clock/stm32mp1-clks.h>
     93    #include <dt-bindings/reset/stm32mp1-resets.h>
     94    dcmi: dcmi@4c006000 {
     95        compatible = "st,stm32-dcmi";
     96        reg = <0x4c006000 0x400>;
     97        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
     98        resets = <&rcc CAMITF_R>;
     99        clocks = <&rcc DCMI>;
    100        clock-names = "mclk";
    101        dmas = <&dmamux1 75 0x400 0x0d>;
    102        dma-names = "tx";
    103
    104        port {
    105             dcmi_0: endpoint {
    106                   remote-endpoint = <&ov5640_0>;
    107                   bus-type = <5>;
    108                   bus-width = <8>;
    109                   hsync-active = <0>;
    110                   vsync-active = <0>;
    111                   pclk-sample = <1>;
    112             };
    113        };
    114    };
    115
    116...