cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,cal.yaml (4415B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/media/ti,cal.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) Device Tree Bindings
      8
      9maintainers:
     10  - Benoit Parrot <bparrot@ti.com>
     11
     12description: |-
     13  The Camera Adaptation Layer (CAL) is a key component for image capture
     14  applications. The capture module provides the system interface and the
     15  processing capability to connect CSI2 image-sensor modules to the
     16  DRA72x device.
     17
     18  CAL supports 2 camera port nodes on MIPI bus.
     19
     20properties:
     21  compatible:
     22    enum:
     23      # for DRA72 controllers
     24      - ti,dra72-cal
     25      # for DRA72 controllers pre ES2.0
     26      - ti,dra72-pre-es2-cal
     27      # for DRA76 controllers
     28      - ti,dra76-cal
     29      # for AM654 controllers
     30      - ti,am654-cal
     31
     32  reg:
     33    minItems: 2
     34    items:
     35      - description: The CAL main register region
     36      - description: The RX Core0 (DPHY0) register region
     37      - description: The RX Core1 (DPHY1) register region
     38
     39  reg-names:
     40    minItems: 2
     41    items:
     42      - const: cal_top
     43      - const: cal_rx_core0
     44      - const: cal_rx_core1
     45
     46  interrupts:
     47    maxItems: 1
     48
     49  ti,camerrx-control:
     50    $ref: "/schemas/types.yaml#/definitions/phandle-array"
     51    items:
     52      - items:
     53          - description: phandle to device control module
     54          - description: offset to the control_camerarx_core register
     55    description:
     56      phandle to the device control module and offset to the
     57      control_camerarx_core register
     58
     59  clocks:
     60    maxItems: 1
     61
     62  clock-names:
     63    const: fck
     64
     65  power-domains:
     66    description:
     67      List of phandle and PM domain specifier as documented in
     68      Documentation/devicetree/bindings/power/power_domain.txt
     69    maxItems: 1
     70
     71  ports:
     72    $ref: /schemas/graph.yaml#/properties/ports
     73
     74    properties:
     75      port@0:
     76        $ref: /schemas/graph.yaml#/$defs/port-base
     77        unevaluatedProperties: false
     78        description: CSI2 Port #0
     79
     80        properties:
     81          endpoint:
     82            $ref: video-interfaces.yaml#
     83            unevaluatedProperties: false
     84
     85            properties:
     86              clock-lanes:
     87                maxItems: 1
     88
     89              data-lanes:
     90                minItems: 1
     91                maxItems: 4
     92
     93      port@1:
     94        $ref: /schemas/graph.yaml#/$defs/port-base
     95        unevaluatedProperties: false
     96        description: CSI2 Port #1
     97
     98        properties:
     99          endpoint:
    100            $ref: video-interfaces.yaml#
    101            unevaluatedProperties: false
    102
    103            properties:
    104              clock-lanes:
    105                maxItems: 1
    106
    107              data-lanes:
    108                minItems: 1
    109                maxItems: 4
    110
    111    required:
    112      - port@0
    113
    114required:
    115  - compatible
    116  - reg
    117  - reg-names
    118  - interrupts
    119  - ti,camerrx-control
    120
    121additionalProperties: false
    122
    123examples:
    124  - |
    125    #include <dt-bindings/interrupt-controller/arm-gic.h>
    126
    127    cal: cal@4845b000 {
    128        compatible = "ti,dra72-cal";
    129        reg = <0x4845B000 0x400>,
    130              <0x4845B800 0x40>,
    131              <0x4845B900 0x40>;
    132        reg-names = "cal_top",
    133                    "cal_rx_core0",
    134                    "cal_rx_core1";
    135        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
    136        ti,camerrx-control = <&scm_conf 0xE94>;
    137
    138        ports {
    139              #address-cells = <1>;
    140              #size-cells = <0>;
    141
    142              csi2_0: port@0 {
    143                    reg = <0>;
    144                    csi2_phy0: endpoint {
    145                           remote-endpoint = <&csi2_cam0>;
    146                           clock-lanes = <0>;
    147                           data-lanes = <1 2>;
    148                    };
    149              };
    150        };
    151    };
    152
    153    i2c {
    154        clock-frequency = <400000>;
    155        #address-cells = <1>;
    156        #size-cells = <0>;
    157
    158        camera-sensor@3c {
    159               compatible = "ovti,ov5640";
    160               reg = <0x3c>;
    161               AVDD-supply = <&reg_2p8v>;
    162               DOVDD-supply = <&reg_1p8v>;
    163               DVDD-supply = <&reg_1p5v>;
    164               clocks = <&clk_ov5640_fixed>;
    165               clock-names = "xclk";
    166
    167               port {
    168                    csi2_cam0: endpoint {
    169                            remote-endpoint = <&csi2_phy0>;
    170                            clock-lanes = <0>;
    171                            data-lanes = <1 2>;
    172                    };
    173               };
    174        };
    175    };
    176
    177...