ti,omap3isp.txt (2093B)
1OMAP 3 ISP Device Tree bindings 2=============================== 3 4The DT definitions can be found in include/dt-bindings/media/omap3-isp.h. 5 6Required properties 7=================== 8 9compatible : must contain "ti,omap3-isp" 10 11reg : the two registers sets (physical address and length) for the 12 ISP. The first set contains the core ISP registers up to 13 the end of the SBL block. The second set contains the 14 CSI PHYs and receivers registers. 15interrupts : the ISP interrupt specifier 16iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP 17syscon : the phandle and register offset to the Complex I/O or CSI-PHY 18 register 19ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430) 20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630) 21#clock-cells : Must be 1 --- the ISP provides two external clocks, 22 cam_xclka and cam_xclkb, at indices 0 and 1, 23 respectively. Please find more information on common 24 clock bindings in ../clock/clock-bindings.txt. 25 26Port nodes (optional) 27--------------------- 28 29More documentation on these bindings is available in 30video-interfaces.txt in the same directory. 31 32reg : The interface: 33 0 - parallel (CCDC) 34 1 - CSIPHY1 -- CSI2C / CCP2B on 3630; 35 CSI1 -- CSIb on 3430 36 2 - CSIPHY2 -- CSI2A / CCP2B on 3630; 37 CSI2 -- CSIa on 3430 38 39Optional properties 40=================== 41 42vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1 43vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2 44 45Endpoint nodes 46-------------- 47 48lane-polarities : lane polarity (required on CSI-2) 49 0 -- not inverted; 1 -- inverted 50data-lanes : an array of data lanes from 1 to 3. The length can 51 be either 1 or 2. (required on CSI-2) 52clock-lanes : the clock lane (from 1 to 3). (required on CSI-2) 53 54 55Example 56======= 57 58 isp@480bc000 { 59 compatible = "ti,omap3-isp"; 60 reg = <0x480bc000 0x12fc 61 0x480bd800 0x0600>; 62 interrupts = <24>; 63 iommus = <&mmu_isp>; 64 syscon = <&scm_conf 0x2f0>; 65 ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; 66 #clock-cells = <1>; 67 ports { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 }; 71 };