xlnx,csi2rxss.yaml (5565B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx MIPI CSI-2 Receiver Subsystem 8 9maintainers: 10 - Vishal Sagar <vishal.sagar@xilinx.com> 11 12description: | 13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 14 traffic from compliant camera sensors and send the output as AXI4 Stream 15 video data for image processing. 16 The subsystem consists of a MIPI D-PHY in slave mode which captures the 17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the 18 packet data. The optional Video Format Bridge (VFB) converts this data to 19 AXI4 Stream video data. 20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem. 21 Please note that this bindings includes only the MIPI CSI-2 Rx controller 22 and Video Format Bridge and not D-PHY. 23 24properties: 25 compatible: 26 items: 27 - enum: 28 - xlnx,mipi-csi2-rx-subsystem-5.0 29 30 reg: 31 maxItems: 1 32 33 interrupts: 34 maxItems: 1 35 36 clocks: 37 description: List of clock specifiers 38 items: 39 - description: AXI Lite clock 40 - description: Video clock 41 42 clock-names: 43 items: 44 - const: lite_aclk 45 - const: video_aclk 46 47 xlnx,csi-pxl-format: 48 description: | 49 This denotes the CSI Data type selected in hw design. 50 Packets other than this data type (except for RAW8 and 51 User defined data types) will be filtered out. 52 Possible values are as below - 53 0x1e - YUV4228B 54 0x1f - YUV42210B 55 0x20 - RGB444 56 0x21 - RGB555 57 0x22 - RGB565 58 0x23 - RGB666 59 0x24 - RGB888 60 0x28 - RAW6 61 0x29 - RAW7 62 0x2a - RAW8 63 0x2b - RAW10 64 0x2c - RAW12 65 0x2d - RAW14 66 0x2e - RAW16 67 0x2f - RAW20 68 $ref: /schemas/types.yaml#/definitions/uint32 69 oneOf: 70 - minimum: 0x1e 71 maximum: 0x24 72 - minimum: 0x28 73 maximum: 0x2f 74 75 xlnx,vfb: 76 type: boolean 77 description: Present when Video Format Bridge is enabled in IP configuration 78 79 xlnx,en-csi-v2-0: 80 type: boolean 81 description: Present if CSI v2 is enabled in IP configuration. 82 83 xlnx,en-vcx: 84 type: boolean 85 description: | 86 When present, there are maximum 16 virtual channels, else only 4. 87 88 xlnx,en-active-lanes: 89 type: boolean 90 description: | 91 Present if the number of active lanes can be re-configured at 92 runtime in the Protocol Configuration Register. Otherwise all lanes, 93 as set in IP configuration, are always active. 94 95 video-reset-gpios: 96 description: Optional specifier for a GPIO that asserts video_aresetn. 97 maxItems: 1 98 99 ports: 100 $ref: /schemas/graph.yaml#/properties/ports 101 102 properties: 103 port@0: 104 $ref: /schemas/graph.yaml#/$defs/port-base 105 description: | 106 Input / sink port node, single endpoint describing the 107 CSI-2 transmitter. 108 109 properties: 110 endpoint: 111 $ref: /schemas/media/video-interfaces.yaml# 112 unevaluatedProperties: false 113 114 properties: 115 data-lanes: 116 description: | 117 This is required only in the sink port 0 endpoint which 118 connects to MIPI CSI-2 source like sensor. 119 The possible values are - 120 1 - For 1 lane enabled in IP. 121 1 2 - For 2 lanes enabled in IP. 122 1 2 3 - For 3 lanes enabled in IP. 123 1 2 3 4 - For 4 lanes enabled in IP. 124 items: 125 - const: 1 126 - const: 2 127 - const: 3 128 - const: 4 129 130 required: 131 - data-lanes 132 133 unevaluatedProperties: false 134 135 port@1: 136 $ref: /schemas/graph.yaml#/properties/port 137 description: | 138 Output / source port node, endpoint describing modules 139 connected the CSI-2 receiver. 140 141required: 142 - compatible 143 - reg 144 - interrupts 145 - clocks 146 - clock-names 147 - ports 148 149allOf: 150 - if: 151 required: 152 - xlnx,vfb 153 then: 154 required: 155 - xlnx,csi-pxl-format 156 else: 157 properties: 158 xlnx,csi-pxl-format: false 159 160 - if: 161 not: 162 required: 163 - xlnx,en-csi-v2-0 164 then: 165 properties: 166 xlnx,en-vcx: false 167 168additionalProperties: false 169 170examples: 171 - | 172 #include <dt-bindings/gpio/gpio.h> 173 xcsi2rxss_1: csi2rx@a0020000 { 174 compatible = "xlnx,mipi-csi2-rx-subsystem-5.0"; 175 reg = <0xa0020000 0x10000>; 176 interrupt-parent = <&gic>; 177 interrupts = <0 95 4>; 178 xlnx,csi-pxl-format = <0x2a>; 179 xlnx,vfb; 180 xlnx,en-active-lanes; 181 xlnx,en-csi-v2-0; 182 xlnx,en-vcx; 183 clock-names = "lite_aclk", "video_aclk"; 184 clocks = <&misc_clk_0>, <&misc_clk_1>; 185 video-reset-gpios = <&gpio 86 GPIO_ACTIVE_LOW>; 186 187 ports { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 port@0 { 192 /* Sink port */ 193 reg = <0>; 194 csiss_in: endpoint { 195 data-lanes = <1 2 3 4>; 196 /* MIPI CSI-2 Camera handle */ 197 remote-endpoint = <&camera_out>; 198 }; 199 }; 200 port@1 { 201 /* Source port */ 202 reg = <1>; 203 csiss_out: endpoint { 204 remote-endpoint = <&vproc_in>; 205 }; 206 }; 207 }; 208 }; 209...