cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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calxeda-ddr-ctrlr.yaml (921B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Calxeda DDR memory controller binding
      8
      9description: |
     10  The Calxeda DDR memory controller is initialised and programmed by the
     11  firmware, but an OS might want to read its registers for error reporting
     12  purposes and to learn about the DRAM topology.
     13
     14maintainers:
     15  - Andre Przywara <andre.przywara@arm.com>
     16
     17properties:
     18  compatible:
     19    enum:
     20      - calxeda,hb-ddr-ctrl
     21      - calxeda,ecx-2000-ddr-ctrl
     22
     23  reg:
     24    maxItems: 1
     25
     26  interrupts:
     27    maxItems: 1
     28
     29required:
     30  - compatible
     31  - reg
     32  - interrupts
     33
     34additionalProperties: false
     35
     36examples:
     37  - |
     38    memory-controller@fff00000 {
     39        compatible = "calxeda,hb-ddr-ctrl";
     40        reg = <0xfff00000 0x1000>;
     41        interrupts = <0 91 4>;
     42    };