cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qca,ath79-ddr-controller.yaml (1624B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
      8
      9maintainers:
     10  - Krzysztof Kozlowski <krzk@kernel.org>
     11
     12description: |
     13  The DDR controller of the AR7xxx and AR9xxx families provides an interface to
     14  flush the FIFO between various devices and the DDR. This is mainly used by
     15  the IRQ controller to flush the FIFO before running the interrupt handler of
     16  such devices.
     17
     18properties:
     19  compatible:
     20    oneOf:
     21      - items:
     22          - const: qca,ar9132-ddr-controller
     23          - const: qca,ar7240-ddr-controller
     24      - items:
     25          - enum:
     26              - qca,ar7100-ddr-controller
     27              - qca,ar7240-ddr-controller
     28
     29  "#qca,ddr-wb-channel-cells":
     30    description: |
     31      Specifies the number of cells needed to encode the write buffer channel
     32      index.
     33    $ref: /schemas/types.yaml#/definitions/uint32
     34    const: 1
     35
     36  reg:
     37    maxItems: 1
     38
     39required:
     40  - compatible
     41  - "#qca,ddr-wb-channel-cells"
     42  - reg
     43
     44additionalProperties: false
     45
     46examples:
     47  - |
     48    ddr_ctrl: memory-controller@18000000 {
     49        compatible = "qca,ar9132-ddr-controller",
     50                     "qca,ar7240-ddr-controller";
     51        reg = <0x18000000 0x100>;
     52
     53        #qca,ddr-wb-channel-cells = <1>;
     54    };
     55
     56    interrupt-controller {
     57        // ...
     58        qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
     59        qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
     60                              <&ddr_ctrl 0>, <&ddr_ctrl 1>;
     61    };