cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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emif.txt (2850B)

      1* EMIF family of TI SDRAM controllers
      2
      3EMIF - External Memory Interface - is an SDRAM controller used in
      4TI SoCs. EMIF supports, based on the IP revision, one or more of
      5DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
      6of the EMIF IP and memory parts attached to it. Certain revisions
      7of the EMIF controller also contain optional ECC support, which
      8corrects one bit errors and detects two bit errors.
      9
     10Required properties:
     11- compatible	: Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
     12  is the IP revision of the specific EMIF instance. For newer controllers,
     13  compatible should be one of the following:
     14  	     "ti,emif-am3352"
     15	     "ti,emif-am4372"
     16	     "ti,emif-dra7xx"
     17	     "ti,emif-keystone"
     18
     19- phy-type	: <u32> indicating the DDR phy type. Following are the
     20  allowed values
     21  <1>	: Attila PHY
     22  <2>	: Intelli PHY
     23
     24- device-handle	: phandle to a "lpddr2" node representing the memory part
     25
     26- ti,hwmods	: For TI hwmods processing and omap device creation
     27  the value shall be "emif<n>" where <n> is the number of the EMIF
     28  instance with base 1.
     29- interrupts	: interrupt used by the controller
     30
     31Required only for "ti,emif-am3352" and "ti,emif-am4372":
     32- sram			: Phandles for generic sram driver nodes,
     33  first should be type 'protect-exec' for the driver to use to copy
     34  and run PM functions, second should be regular pool to be used for
     35  data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
     36  for more details.
     37
     38Optional properties:
     39- cs1-used		: Have this property if CS1 of this EMIF
     40  instance has a memory part attached to it. If there is a memory
     41  part attached to CS1, it should be the same type as the one on CS0,
     42  so there is no need to give the details of this memory part.
     43
     44- cal-resistor-per-cs	: Have this property if the board has one
     45  calibration resistor per chip-select.
     46
     47- hw-caps-read-idle-ctrl: Have this property if the controller
     48  supports read idle window programming
     49
     50- hw-caps-dll-calib-ctrl: Have this property if the controller
     51  supports dll calibration control
     52
     53- hw-caps-ll-interface	: Have this property if the controller
     54  has a low latency interface and corresponding interrupt events
     55
     56- hw-caps-temp-alert	: Have this property if the controller
     57  has capability for generating SDRAM temperature alerts
     58
     59-Examples:
     60
     61emif1: emif@4c000000 {
     62	compatible	= "ti,emif-4d";
     63	ti,hwmods	= "emif2";
     64	phy-type	= <1>;
     65	device-handle	= <&elpida_ECB240ABACN>;
     66	cs1-used;
     67	hw-caps-read-idle-ctrl;
     68	hw-caps-ll-interface;
     69	hw-caps-temp-alert;
     70};
     71
     72/* From am33xx.dtsi */
     73emif: emif@4c000000 {
     74        compatible = "ti,emif-am3352";
     75        reg =   <0x4C000000 0x1000>;
     76        sram = <&pm_sram_code
     77                &pm_sram_data>;
     78};
     79
     80emif1: emif@4c000000 {
     81	compatible = "ti,emif-dra7xx";
     82	reg = <0x4c000000 0x200>;
     83	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
     84};