cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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brcm,bcm6318-gpio-sysctl.yaml (4424B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings
      8
      9maintainers:
     10  - Álvaro Fernández Rojas <noltari@gmail.com>
     11  - Jonas Gorski <jonas.gorski@gmail.com>
     12
     13description:
     14  Broadcom BCM6318 SoC GPIO system controller which provides a register map
     15  for controlling the GPIO and pins of the SoC.
     16
     17properties:
     18  "#address-cells": true
     19
     20  "#size-cells": true
     21
     22  compatible:
     23    items:
     24      - const: brcm,bcm6318-gpio-sysctl
     25      - const: syscon
     26      - const: simple-mfd
     27
     28  ranges:
     29    maxItems: 1
     30
     31  reg:
     32    maxItems: 1
     33
     34patternProperties:
     35  "^gpio@[0-9a-f]+$":
     36    # Child node
     37    type: object
     38    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
     39    description:
     40      GPIO controller for the SoC GPIOs. This child node definition
     41      should follow the bindings specified in
     42      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
     43
     44  "^pinctrl@[0-9a-f]+$":
     45    # Child node
     46    type: object
     47    $ref: "../pinctrl/brcm,bcm6318-pinctrl.yaml"
     48    description:
     49      Pin controller for the SoC pins. This child node definition
     50      should follow the bindings specified in
     51      Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml.
     52
     53required:
     54  - "#address-cells"
     55  - compatible
     56  - ranges
     57  - reg
     58  - "#size-cells"
     59
     60additionalProperties: false
     61
     62examples:
     63  - |
     64    syscon@10000080 {
     65      #address-cells = <1>;
     66      #size-cells = <1>;
     67      compatible = "brcm,bcm6318-gpio-sysctl", "syscon", "simple-mfd";
     68      reg = <0x10000080 0x80>;
     69      ranges = <0 0x10000080 0x80>;
     70
     71      gpio@0 {
     72        compatible = "brcm,bcm6318-gpio";
     73        reg-names = "dirout", "dat";
     74        reg = <0x0 0x8>, <0x8 0x8>;
     75
     76        gpio-controller;
     77        gpio-ranges = <&pinctrl 0 0 50>;
     78        #gpio-cells = <2>;
     79      };
     80
     81      pinctrl: pinctrl@10 {
     82        compatible = "brcm,bcm6318-pinctrl";
     83        reg = <0x18 0x10>, <0x54 0x18>;
     84
     85        pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
     86          function = "ephy0_spd_led";
     87          pins = "gpio0";
     88        };
     89
     90        pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
     91          function = "ephy1_spd_led";
     92          pins = "gpio1";
     93        };
     94
     95        pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
     96          function = "ephy2_spd_led";
     97          pins = "gpio2";
     98        };
     99
    100        pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
    101          function = "ephy3_spd_led";
    102          pins = "gpio3";
    103        };
    104
    105        pinctrl_ephy0_act_led: ephy0_act_led-pins {
    106          function = "ephy0_act_led";
    107          pins = "gpio4";
    108        };
    109
    110        pinctrl_ephy1_act_led: ephy1_act_led-pins {
    111          function = "ephy1_act_led";
    112          pins = "gpio5";
    113        };
    114
    115        pinctrl_ephy2_act_led: ephy2_act_led-pins {
    116          function = "ephy2_act_led";
    117          pins = "gpio6";
    118        };
    119
    120        pinctrl_ephy3_act_led: ephy3_act_led-pins {
    121          function = "ephy3_act_led";
    122          pins = "gpio7";
    123        };
    124
    125        pinctrl_serial_led: serial_led-pins {
    126          pinctrl_serial_led_data: serial_led_data-pins {
    127            function = "serial_led_data";
    128            pins = "gpio6";
    129          };
    130
    131          pinctrl_serial_led_clk: serial_led_clk-pins {
    132            function = "serial_led_clk";
    133            pins = "gpio7";
    134          };
    135        };
    136
    137        pinctrl_inet_act_led: inet_act_led-pins {
    138          function = "inet_act_led";
    139          pins = "gpio8";
    140        };
    141
    142        pinctrl_inet_fail_led: inet_fail_led-pins {
    143          function = "inet_fail_led";
    144          pins = "gpio9";
    145        };
    146
    147        pinctrl_dsl_led: dsl_led-pins {
    148          function = "dsl_led";
    149          pins = "gpio10";
    150        };
    151
    152        pinctrl_post_fail_led: post_fail_led-pins {
    153          function = "post_fail_led";
    154          pins = "gpio11";
    155        };
    156
    157        pinctrl_wlan_wps_led: wlan_wps_led-pins {
    158          function = "wlan_wps_led";
    159          pins = "gpio12";
    160        };
    161
    162        pinctrl_usb_pwron: usb_pwron-pins {
    163          function = "usb_pwron";
    164          pins = "gpio13";
    165        };
    166
    167        pinctrl_usb_device_led: usb_device_led-pins {
    168          function = "usb_device_led";
    169          pins = "gpio13";
    170        };
    171
    172        pinctrl_usb_active: usb_active-pins {
    173          function = "usb_active";
    174          pins = "gpio40";
    175        };
    176      };
    177    };