cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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brcm,bcm6328-gpio-sysctl.yaml (4034B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Broadcom BCM6328 GPIO System Controller Device Tree Bindings
      8
      9maintainers:
     10  - Álvaro Fernández Rojas <noltari@gmail.com>
     11  - Jonas Gorski <jonas.gorski@gmail.com>
     12
     13description:
     14  Broadcom BCM6328 SoC GPIO system controller which provides a register map
     15  for controlling the GPIO and pins of the SoC.
     16
     17properties:
     18  "#address-cells": true
     19
     20  "#size-cells": true
     21
     22  compatible:
     23    items:
     24      - const: brcm,bcm6328-gpio-sysctl
     25      - const: syscon
     26      - const: simple-mfd
     27
     28  ranges:
     29    maxItems: 1
     30
     31  reg:
     32    maxItems: 1
     33
     34patternProperties:
     35  "^gpio@[0-9a-f]+$":
     36    # Child node
     37    type: object
     38    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
     39    description:
     40      GPIO controller for the SoC GPIOs. This child node definition
     41      should follow the bindings specified in
     42      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
     43
     44  "^pinctrl@[0-9a-f]+$":
     45    # Child node
     46    type: object
     47    $ref: "../pinctrl/brcm,bcm6328-pinctrl.yaml"
     48    description:
     49      Pin controller for the SoC pins. This child node definition
     50      should follow the bindings specified in
     51      Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml.
     52
     53required:
     54  - "#address-cells"
     55  - compatible
     56  - ranges
     57  - reg
     58  - "#size-cells"
     59
     60additionalProperties: false
     61
     62examples:
     63  - |
     64    syscon@10000080 {
     65      #address-cells = <1>;
     66      #size-cells = <1>;
     67      compatible = "brcm,bcm6328-gpio-sysctl", "syscon", "simple-mfd";
     68      reg = <0x10000080 0x80>;
     69      ranges = <0 0x10000080 0x80>;
     70
     71      gpio@0 {
     72        compatible = "brcm,bcm6328-gpio";
     73        reg-names = "dirout", "dat";
     74        reg = <0x0 0x8>, <0x8 0x8>;
     75
     76        gpio-controller;
     77        gpio-ranges = <&pinctrl 0 0 32>;
     78        #gpio-cells = <2>;
     79      };
     80
     81      pinctrl: pinctrl@18 {
     82        compatible = "brcm,bcm6328-pinctrl";
     83        reg = <0x18 0x10>;
     84
     85        pinctrl_serial_led: serial_led-pins {
     86          pinctrl_serial_led_data: serial_led_data-pins {
     87            function = "serial_led_data";
     88            pins = "gpio6";
     89          };
     90
     91          pinctrl_serial_led_clk: serial_led_clk-pins {
     92            function = "serial_led_clk";
     93            pins = "gpio7";
     94          };
     95        };
     96
     97        pinctrl_inet_act_led: inet_act_led-pins {
     98          function = "inet_act_led";
     99          pins = "gpio11";
    100        };
    101
    102        pinctrl_pcie_clkreq: pcie_clkreq-pins {
    103          function = "pcie_clkreq";
    104          pins = "gpio16";
    105        };
    106
    107        pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
    108          function = "led";
    109          pins = "gpio17";
    110        };
    111
    112        pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
    113          function = "led";
    114          pins = "gpio18";
    115        };
    116
    117        pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
    118          function = "led";
    119          pins = "gpio19";
    120        };
    121
    122        pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
    123          function = "led";
    124          pins = "gpio20";
    125        };
    126
    127        pinctrl_ephy0_act_led: ephy0_act_led-pins {
    128          function = "ephy0_act_led";
    129          pins = "gpio25";
    130        };
    131
    132        pinctrl_ephy1_act_led: ephy1_act_led-pins {
    133          function = "ephy1_act_led";
    134          pins = "gpio26";
    135        };
    136
    137        pinctrl_ephy2_act_led: ephy2_act_led-pins {
    138          function = "ephy2_act_led";
    139          pins = "gpio27";
    140        };
    141
    142        pinctrl_ephy3_act_led: ephy3_act_led-pins {
    143          function = "ephy3_act_led";
    144          pins = "gpio28";
    145        };
    146
    147        pinctrl_hsspi_cs1: hsspi_cs1-pins {
    148          function = "hsspi_cs1";
    149          pins = "hsspi_cs1";
    150        };
    151
    152        pinctrl_usb_port1_device: usb_port1_device-pins {
    153          function = "usb_device_port";
    154          pins = "usb_port1";
    155        };
    156
    157        pinctrl_usb_port1_host: usb_port1_host-pins {
    158          function = "usb_host_port";
    159          pins = "usb_port1";
    160        };
    161      };
    162    };