cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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delta,tn48m-cpld.yaml (1954B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mfd/delta,tn48m-cpld.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Delta Networks TN48M CPLD controller
      8
      9maintainers:
     10  - Robert Marko <robert.marko@sartura.hr>
     11
     12description: |
     13  Lattice CPLD onboard the TN48M switches is used for system
     14  management.
     15
     16  It provides information about the hardware model, revision,
     17  PSU status etc.
     18
     19  It is also being used as a GPIO expander and reset controller
     20  for the switch MAC-s and other peripherals.
     21
     22properties:
     23  compatible:
     24    const: delta,tn48m-cpld
     25
     26  reg:
     27    description:
     28      I2C device address.
     29    maxItems: 1
     30
     31  "#address-cells":
     32    const: 1
     33
     34  "#size-cells":
     35    const: 0
     36
     37required:
     38  - compatible
     39  - reg
     40  - "#address-cells"
     41  - "#size-cells"
     42
     43patternProperties:
     44  "^gpio(@[0-9a-f]+)?$":
     45    $ref: ../gpio/delta,tn48m-gpio.yaml
     46
     47  "^reset-controller?$":
     48    $ref: ../reset/delta,tn48m-reset.yaml
     49
     50additionalProperties: false
     51
     52examples:
     53  - |
     54    i2c {
     55        #address-cells = <1>;
     56        #size-cells = <0>;
     57
     58        cpld@41 {
     59            compatible = "delta,tn48m-cpld";
     60            reg = <0x41>;
     61            #address-cells = <1>;
     62            #size-cells = <0>;
     63
     64            gpio@31 {
     65                compatible = "delta,tn48m-gpo";
     66                reg = <0x31>;
     67                gpio-controller;
     68                #gpio-cells = <2>;
     69            };
     70
     71            gpio@3a {
     72                compatible = "delta,tn48m-gpi";
     73                reg = <0x3a>;
     74                gpio-controller;
     75                #gpio-cells = <2>;
     76            };
     77
     78            gpio@40 {
     79                compatible = "delta,tn48m-gpi";
     80                reg = <0x40>;
     81                gpio-controller;
     82                #gpio-cells = <2>;
     83            };
     84
     85            reset-controller {
     86              compatible = "delta,tn48m-reset";
     87              #reset-cells = <1>;
     88            };
     89        };
     90    };