cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hisilicon,hi655x.txt (1188B)

      1Hisilicon Hi655x Power Management Integrated Circuit (PMIC)
      2
      3The hardware layout for access PMIC Hi655x from AP SoC Hi6220.
      4Between PMIC Hi655x and Hi6220, the physical signal channel is SSI.
      5We can use memory-mapped I/O to communicate.
      6
      7+----------------+             +-------------+
      8|                |             |             |
      9|    Hi6220      |   SSI bus   |   Hi655x    |
     10|                |-------------|             |
     11|                |(REGMAP_MMIO)|             |
     12+----------------+             +-------------+
     13
     14Required properties:
     15- compatible:           Should be "hisilicon,hi655x-pmic".
     16- reg:                  Base address of PMIC on Hi6220 SoC.
     17- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
     18- pmic-gpios:           The GPIO used by PMIC IRQ.
     19- #clock-cells:		From common clock binding; shall be set to 0
     20
     21Optional properties:
     22- clock-output-names: From common clock binding to override the
     23  default output clock name
     24
     25Example:
     26	pmic: pmic@f8000000 {
     27		compatible = "hisilicon,hi655x-pmic";
     28		reg = <0x0 0xf8000000 0x0 0x1000>;
     29		interrupt-controller;
     30		#interrupt-cells = <2>;
     31		pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
     32		#clock-cells = <0>;
     33	}