cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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palmas.txt (1129B)


      1* palmas device tree bindings
      2
      3The TI palmas family current members :-
      4twl6035 (palmas)
      5twl6037 (palmas)
      6tps65913 (palmas)
      7tps65914 (palmas)
      8tps659038
      9tps65917
     10
     11Required properties:
     12- compatible : Should be from the list
     13  ti,twl6035
     14  ti,twl6036
     15  ti,twl6037
     16  ti,tps65913
     17  ti,tps65914
     18  ti,tps80036
     19  ti,tps659038
     20  ti,tps65917
     21and also the generic series names
     22  ti,palmas
     23- interrupt-controller : palmas has its own internal IRQs
     24- #interrupt-cells : should be set to 2 for IRQ number and flags
     25  The first cell is the IRQ number.
     26  The second cell is the flags, encoded as the trigger masks from
     27  Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
     28
     29Optional properties:
     30  ti,mux-padX : set the pad register X (1-2) to the correct muxing for the
     31		hardware, if not set will use muxing in OTP.
     32
     33Example:
     34
     35palmas {
     36	compatible = "ti,twl6035", "ti,palmas";
     37	reg = <0x48>
     38	interrupt-parent = <&intc>;
     39	interrupt-controller;
     40	#interrupt-cells = <2>;
     41
     42	ti,mux-pad1 = <0>;
     43	ti,mux-pad2 = <0>;
     44
     45	#address-cells = <1>;
     46	#size-cells = <0>;
     47
     48	pmic {
     49		compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
     50		....
     51	};
     52}