cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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samsung,exynos5433-lpass.yaml (3070B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mfd/samsung,exynos5433-lpass.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
      8
      9maintainers:
     10  - Krzysztof Kozlowski <krzk@kernel.org>
     11  - Sylwester Nawrocki <s.nawrocki@samsung.com>
     12
     13properties:
     14  compatible:
     15    const: samsung,exynos5433-lpass
     16
     17  '#address-cells':
     18    const: 1
     19
     20  clocks:
     21    maxItems: 1
     22
     23  clock-names:
     24    items:
     25      - const: sfr0_ctrl
     26
     27  power-domains:
     28    maxItems: 1
     29
     30  ranges: true
     31
     32  reg:
     33    minItems: 2
     34    maxItems: 2
     35
     36  '#size-cells':
     37    const: 1
     38
     39patternProperties:
     40  "^dma-controller@[0-9a-f]+$":
     41    $ref: /schemas/dma/arm,pl330.yaml
     42
     43  "^i2s@[0-9a-f]+$":
     44    $ref: /schemas/sound/samsung-i2s.yaml
     45
     46  "^serial@[0-9a-f]+$":
     47    $ref: /schemas/serial/samsung_uart.yaml
     48
     49required:
     50  - compatible
     51  - '#address-cells'
     52  - clocks
     53  - clock-names
     54  - ranges
     55  - reg
     56  - '#size-cells'
     57
     58additionalProperties: false
     59
     60examples:
     61  - |
     62    #include <dt-bindings/clock/exynos5433.h>
     63    #include <dt-bindings/interrupt-controller/arm-gic.h>
     64
     65    audio-subsystem@11400000 {
     66        compatible = "samsung,exynos5433-lpass";
     67        reg = <0x11400000 0x100>, <0x11500000 0x08>;
     68        clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
     69        clock-names = "sfr0_ctrl";
     70        power-domains = <&pd_aud>;
     71        #address-cells = <1>;
     72        #size-cells = <1>;
     73        ranges;
     74
     75        dma-controller@11420000 {
     76            compatible = "arm,pl330", "arm,primecell";
     77            reg = <0x11420000 0x1000>;
     78            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
     79            clocks = <&cmu_aud CLK_ACLK_DMAC>;
     80            clock-names = "apb_pclk";
     81            #dma-cells = <1>;
     82            dma-channels = <8>;
     83            dma-requests = <32>;
     84            power-domains = <&pd_aud>;
     85        };
     86
     87        i2s@11440000 {
     88            compatible = "samsung,exynos7-i2s";
     89            reg = <0x11440000 0x100>;
     90            dmas = <&adma 0>, <&adma 2>;
     91            dma-names = "tx", "rx";
     92            interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
     93            #address-cells = <1>;
     94            #size-cells = <0>;
     95            clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
     96                     <&cmu_aud CLK_SCLK_AUD_I2S>,
     97                     <&cmu_aud CLK_SCLK_I2S_BCLK>;
     98            clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
     99            #clock-cells = <1>;
    100            pinctrl-names = "default";
    101            pinctrl-0 = <&i2s0_bus>;
    102            power-domains = <&pd_aud>;
    103            #sound-dai-cells = <1>;
    104        };
    105
    106        serial@11460000 {
    107            compatible = "samsung,exynos5433-uart";
    108            reg = <0x11460000 0x100>;
    109            interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
    110            clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
    111                     <&cmu_aud CLK_SCLK_AUD_UART>;
    112            clock-names = "uart", "clk_uart_baud0";
    113            pinctrl-names = "default";
    114            pinctrl-0 = <&uart_aud_bus>;
    115            power-domains = <&pd_aud>;
    116        };
    117    };