cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,stm32-timers.yaml (3532B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: STMicroelectronics STM32 Timers bindings
      8
      9description: |
     10  This hardware block provides 3 types of timer along with PWM functionality:
     11    - advanced-control timers consist of a 16-bit auto-reload counter driven
     12      by a programmable prescaler, break input feature, PWM outputs and
     13      complementary PWM outputs channels.
     14    - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
     15      driven by a programmable prescaler and PWM outputs.
     16    - basic timers consist of a 16-bit auto-reload counter driven by a
     17      programmable prescaler.
     18
     19maintainers:
     20  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
     21
     22properties:
     23  compatible:
     24    const: st,stm32-timers
     25
     26  reg:
     27    maxItems: 1
     28
     29  clocks:
     30    maxItems: 1
     31
     32  clock-names:
     33    items:
     34      - const: int
     35
     36  reset:
     37    maxItems: 1
     38
     39  dmas:
     40    minItems: 1
     41    maxItems: 7
     42
     43  dma-names:
     44    items:
     45      enum: [ ch1, ch2, ch3, ch4, up, trig, com ]
     46    minItems: 1
     47    maxItems: 7
     48
     49  "#address-cells":
     50    const: 1
     51
     52  "#size-cells":
     53    const: 0
     54
     55  pwm:
     56    type: object
     57
     58    properties:
     59      compatible:
     60        const: st,stm32-pwm
     61
     62      "#pwm-cells":
     63        const: 3
     64
     65      st,breakinput:
     66        description:
     67          One or two <index level filter> to describe break input
     68          configurations.
     69        $ref: /schemas/types.yaml#/definitions/uint32-matrix
     70        items:
     71          items:
     72            - description: |
     73                "index" indicates on which break input (0 or 1) the
     74                configuration should be applied.
     75              enum: [0, 1]
     76            - description: |
     77                "level" gives the active level (0=low or 1=high) of the
     78                input signal for this configuration
     79              enum: [0, 1]
     80            - description: |
     81                "filter" gives the filtering value (up to 15) to be applied.
     82              maximum: 15
     83        minItems: 1
     84        maxItems: 2
     85
     86    required:
     87      - "#pwm-cells"
     88      - compatible
     89
     90patternProperties:
     91  "^timer@[0-9]+$":
     92    type: object
     93
     94    properties:
     95      compatible:
     96        enum:
     97          - st,stm32-timer-trigger
     98          - st,stm32h7-timer-trigger
     99
    100      reg:
    101        description: Identify trigger hardware block.
    102        items:
    103          minimum: 0
    104          maximum: 16
    105
    106    required:
    107      - compatible
    108      - reg
    109
    110  counter:
    111    type: object
    112
    113    properties:
    114      compatible:
    115        const: st,stm32-timer-counter
    116
    117    required:
    118      - compatible
    119
    120required:
    121  - compatible
    122  - reg
    123  - clocks
    124  - clock-names
    125
    126additionalProperties: false
    127
    128examples:
    129  - |
    130    #include <dt-bindings/clock/stm32mp1-clks.h>
    131    timers2: timer@40000000 {
    132      #address-cells = <1>;
    133      #size-cells = <0>;
    134      compatible = "st,stm32-timers";
    135      reg = <0x40000000 0x400>;
    136      clocks = <&rcc TIM2_K>;
    137      clock-names = "int";
    138      dmas = <&dmamux1 18 0x400 0x1>,
    139             <&dmamux1 19 0x400 0x1>,
    140             <&dmamux1 20 0x400 0x1>,
    141             <&dmamux1 21 0x400 0x1>,
    142             <&dmamux1 22 0x400 0x1>;
    143      dma-names = "ch1", "ch2", "ch3", "ch4", "up";
    144      pwm {
    145        compatible = "st,stm32-pwm";
    146        #pwm-cells = <3>;
    147        st,breakinput = <0 1 5>;
    148      };
    149      timer@1 {
    150        compatible = "st,stm32-timer-trigger";
    151        reg = <1>;
    152      };
    153      counter {
    154        compatible = "st,stm32-timer-counter";
    155      };
    156    };
    157
    158...