cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pistachio.txt (1097B)

      1Imagination Pistachio SoC
      2=========================
      3
      4Required properties:
      5--------------------
      6 - compatible: Must include "img,pistachio".
      7
      8CPU nodes:
      9----------
     10A "cpus" node is required.  Required properties:
     11 - #address-cells: Must be 1.
     12 - #size-cells: Must be 0.
     13A CPU sub-node is also required for at least CPU 0.  Since the topology may
     14be probed via CPS, it is not necessary to specify secondary CPUs.  Required
     15propertis:
     16 - device_type: Must be "cpu".
     17 - compatible: Must be "mti,interaptiv".
     18 - reg: CPU number.
     19 - clocks: Must include the CPU clock.  See ../../clock/clock-bindings.txt for
     20   details on clock bindings.
     21Example:
     22	cpus {
     23		#address-cells = <1>;
     24		#size-cells = <0>;
     25
     26		cpu0: cpu@0 {
     27			device_type = "cpu";
     28			compatible = "mti,interaptiv";
     29			reg = <0>;
     30			clocks = <&clk_core CLK_MIPS>;
     31		};
     32	};
     33
     34
     35Boot protocol:
     36--------------
     37In accordance with the MIPS UHI specification[1], the bootloader must pass the
     38following arguments to the kernel:
     39 - $a0: -2.
     40 - $a1: KSEG0 address of the flattened device-tree blob.
     41
     42[1] http://prplfoundation.org/wiki/MIPS_documentation