cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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eeprom-93xx46.yaml (1453B)


      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/misc/eeprom-93xx46.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Microchip 93xx46 SPI compatible EEPROM family dt bindings
      8
      9maintainers:
     10  - Cory Tusar <cory.tusar@pid1solutions.com>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - atmel,at93c46
     16      - atmel,at93c46d
     17      - atmel,at93c56
     18      - atmel,at93c66
     19      - eeprom-93xx46
     20      - microchip,93lc46b
     21
     22  data-size:
     23    description: number of data bits per word
     24    $ref: /schemas/types.yaml#/definitions/uint32
     25    enum: [8, 16]
     26
     27  reg:
     28    description: chip select of EEPROM
     29    maxItems: 1
     30
     31  spi-max-frequency: true
     32  spi-cs-high: true
     33
     34  read-only:
     35    description:
     36      parameter-less property which disables writes to the EEPROM
     37    type: boolean
     38
     39  select-gpios:
     40    description:
     41      specifies the GPIO that needs to be asserted prior to each access
     42      of EEPROM (e.g. for SPI bus multiplexing)
     43    maxItems: 1
     44
     45
     46required:
     47  - compatible
     48  - reg
     49  - data-size
     50  - spi-max-frequency
     51
     52additionalProperties: false
     53
     54examples:
     55  - |
     56    #include <dt-bindings/gpio/gpio.h>
     57
     58    spi {
     59      #address-cells = <1>;
     60      #size-cells = <0>;
     61
     62      eeprom@0 {
     63        compatible = "eeprom-93xx46";
     64        reg = <0>;
     65        spi-max-frequency = <1000000>;
     66        spi-cs-high;
     67        data-size = <8>;
     68        select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
     69      };
     70    };