cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amlogic,meson-mx-sdio.txt (1699B)

      1* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
      2
      3The highspeed MMC host controller on Amlogic SoCs provides an interface
      4for MMC, SD, SDIO and SDHC types of memory cards.
      5
      6Supported maximum speeds are the ones of the eMMC standard 4.41 as well
      7as the speed of SD standard 2.0.
      8
      9The hardware provides an internal "mux" which allows up to three slots
     10to be controlled. Only one slot can be accessed at a time.
     11
     12Required properties:
     13 - compatible : must be one of
     14	- "amlogic,meson8-sdio"
     15	- "amlogic,meson8b-sdio"
     16	along with the generic "amlogic,meson-mx-sdio"
     17 - reg : mmc controller base registers
     18 - interrupts : mmc controller interrupt
     19 - #address-cells : must be 1
     20 - size-cells : must be 0
     21 - clocks : phandle to clock providers
     22 - clock-names : must contain "core" and "clkin"
     23
     24Required child nodes:
     25A node for each slot provided by the MMC controller is required.
     26NOTE: due to a driver limitation currently only one slot (= child node)
     27      is supported!
     28
     29Required properties on each child node (= slot):
     30 - compatible : must be "mmc-slot" (see mmc.txt within this directory)
     31 - reg : the slot (or "port") ID
     32
     33Optional properties on each child node (= slot):
     34 - bus-width : must be 1 or 4 (8-bit bus is not supported)
     35 - for cd and all other additional generic mmc parameters
     36   please refer to mmc.txt within this directory
     37
     38Examples:
     39	mmc@c1108c20 {
     40		compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
     41		reg = <0xc1108c20 0x20>;
     42		interrupts = <0 28 1>;
     43		#address-cells = <1>;
     44		#size-cells = <0>;
     45		clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
     46		clock-names = "core", "clkin";
     47
     48		slot@1 {
     49			compatible = "mmc-slot";
     50			reg = <1>;
     51
     52			bus-width = <4>;
     53		};
     54	};