marvell,xenon-sdhci.yaml (7970B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Marvell Xenon SDHCI Controller 8 9description: | 10 This file documents differences between the core MMC properties described by 11 mmc-controller.yaml and the properties used by the Xenon implementation. 12 13 Multiple SDHCs might be put into a single Xenon IP, to save size and cost. 14 Each SDHC is independent and owns independent resources, such as register 15 sets, clock and PHY. 16 17 Each SDHC should have an independent device tree node. 18 19maintainers: 20 - Ulf Hansson <ulf.hansson@linaro.org> 21 22properties: 23 compatible: 24 oneOf: 25 - enum: 26 - marvell,armada-cp110-sdhci 27 - marvell,armada-ap806-sdhci 28 29 - items: 30 - const: marvell,armada-ap807-sdhci 31 - const: marvell,armada-ap806-sdhci 32 33 - items: 34 - const: marvell,armada-3700-sdhci 35 - const: marvell,sdhci-xenon 36 37 reg: 38 minItems: 1 39 maxItems: 2 40 description: | 41 For "marvell,armada-3700-sdhci", two register areas. The first one 42 for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD 43 Voltage Control register. Please follow the examples with compatible 44 "marvell,armada-3700-sdhci" in below. 45 Please also check property marvell,pad-type in below. 46 47 For other compatible strings, one register area for Xenon IP. 48 49 clocks: 50 minItems: 1 51 maxItems: 2 52 53 clock-names: 54 minItems: 1 55 items: 56 - const: core 57 - const: axi 58 59 interrupts: 60 maxItems: 1 61 62 marvell,xenon-sdhc-id: 63 $ref: /schemas/types.yaml#/definitions/uint32 64 minimum: 0 65 maximum: 7 66 description: | 67 Indicate the corresponding bit index of current SDHC in SDHC System 68 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to 69 enable/disable current SDHC. 70 71 marvell,xenon-phy-type: 72 $ref: /schemas/types.yaml#/definitions/string 73 enum: 74 - "emmc 5.1 phy" 75 - "emmc 5.0 phy" 76 description: | 77 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set: 78 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default 79 choice if this property is not provided. To select eMMC 5.0 PHY, set: 80 marvell,xenon-phy-type = "emmc 5.0 phy" 81 82 All those types of PHYs can support eMMC, SD and SDIO. Please note that 83 this property only presents the type of PHY. It doesn't stand for the 84 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean 85 that this Xenon SDHC only supports eMMC 5.1. 86 87 marvell,xenon-phy-znr: 88 $ref: /schemas/types.yaml#/definitions/uint32 89 minimum: 0 90 maximum: 0x1f 91 default: 0xf 92 description: | 93 Set PHY ZNR value. 94 Only available for eMMC PHY. 95 96 marvell,xenon-phy-zpr: 97 $ref: /schemas/types.yaml#/definitions/uint32 98 minimum: 0 99 maximum: 0x1f 100 default: 0xf 101 description: | 102 Set PHY ZPR value. 103 Only available for eMMC PHY. 104 105 marvell,xenon-phy-nr-success-tun: 106 $ref: /schemas/types.yaml#/definitions/uint32 107 minimum: 1 108 maximum: 7 109 default: 0x4 110 description: | 111 Set the number of required consecutive successful sampling points 112 used to identify a valid sampling window, in tuning process. 113 114 marvell,xenon-phy-tun-step-divider: 115 $ref: /schemas/types.yaml#/definitions/uint32 116 default: 64 117 description: | 118 Set the divider for calculating TUN_STEP. 119 120 marvell,xenon-phy-slow-mode: 121 type: boolean 122 description: | 123 If this property is selected, transfers will bypass PHY. 124 Only available when bus frequency lower than 55MHz in SDR mode. 125 Disabled by default. Please only try this property if timing issues 126 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, 127 SD Default Speed and HS mode and eMMC legacy speed mode. 128 129 marvell,xenon-tun-count: 130 $ref: /schemas/types.yaml#/definitions/uint32 131 default: 0x9 132 description: | 133 Xenon SDHC SoC usually doesn't provide re-tuning counter in 134 Capabilities Register 3 Bit[11:8]. 135 This property provides the re-tuning counter. 136 137allOf: 138 - $ref: mmc-controller.yaml# 139 - if: 140 properties: 141 compatible: 142 contains: 143 const: marvell,armada-3700-sdhci 144 145 then: 146 properties: 147 reg: 148 items: 149 - description: Xenon IP registers 150 - description: Armada 3700 SoC PHY PAD Voltage Control register 151 152 marvell,pad-type: 153 $ref: /schemas/types.yaml#/definitions/string 154 enum: 155 - sd 156 - fixed-1-8v 157 description: | 158 Type of Armada 3700 SoC PHY PAD Voltage Controller register. 159 If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning 160 and is switched to 1.8V when later in higher speed mode. 161 If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for 162 eMMC. 163 Please follow the examples with compatible 164 "marvell,armada-3700-sdhci" in below. 165 166 required: 167 - marvell,pad-type 168 169 - if: 170 properties: 171 compatible: 172 contains: 173 enum: 174 - marvell,armada-cp110-sdhci 175 - marvell,armada-ap807-sdhci 176 - marvell,armada-ap806-sdhci 177 178 then: 179 properties: 180 clocks: 181 minItems: 2 182 183 clock-names: 184 items: 185 - const: core 186 - const: axi 187 188 189required: 190 - compatible 191 - reg 192 - clocks 193 - clock-names 194 195unevaluatedProperties: false 196 197examples: 198 - | 199 // For eMMC 200 #include <dt-bindings/interrupt-controller/arm-gic.h> 201 #include <dt-bindings/interrupt-controller/irq.h> 202 203 mmc@aa0000 { 204 compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci"; 205 reg = <0xaa0000 0x1000>; 206 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&emmc_clk 0>, <&axi_clk 0>; 208 clock-names = "core", "axi"; 209 bus-width = <4>; 210 marvell,xenon-phy-slow-mode; 211 marvell,xenon-tun-count = <11>; 212 non-removable; 213 no-sd; 214 no-sdio; 215 216 /* Vmmc and Vqmmc are both fixed */ 217 }; 218 219 - | 220 // For SD/SDIO 221 #include <dt-bindings/interrupt-controller/arm-gic.h> 222 #include <dt-bindings/interrupt-controller/irq.h> 223 224 mmc@ab0000 { 225 compatible = "marvell,armada-cp110-sdhci"; 226 reg = <0xab0000 0x1000>; 227 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 228 vqmmc-supply = <&sd_vqmmc_regulator>; 229 vmmc-supply = <&sd_vmmc_regulator>; 230 clocks = <&sdclk 0>, <&axi_clk 0>; 231 clock-names = "core", "axi"; 232 bus-width = <4>; 233 marvell,xenon-tun-count = <9>; 234 }; 235 236 - | 237 // For eMMC with compatible "marvell,armada-3700-sdhci": 238 #include <dt-bindings/interrupt-controller/arm-gic.h> 239 #include <dt-bindings/interrupt-controller/irq.h> 240 241 mmc@aa0000 { 242 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; 243 reg = <0xaa0000 0x1000>, 244 <0x17808 0x4>; 245 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&emmcclk 0>; 247 clock-names = "core"; 248 bus-width = <8>; 249 mmc-ddr-1_8v; 250 mmc-hs400-1_8v; 251 non-removable; 252 no-sd; 253 no-sdio; 254 255 /* Vmmc and Vqmmc are both fixed */ 256 257 marvell,pad-type = "fixed-1-8v"; 258 }; 259 260 - | 261 // For SD/SDIO with compatible "marvell,armada-3700-sdhci": 262 #include <dt-bindings/interrupt-controller/arm-gic.h> 263 #include <dt-bindings/interrupt-controller/irq.h> 264 265 mmc@ab0000 { 266 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; 267 reg = <0xab0000 0x1000>, 268 <0x17808 0x4>; 269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 270 vqmmc-supply = <&sd_regulator>; 271 /* Vmmc is fixed */ 272 clocks = <&sdclk 0>; 273 clock-names = "core"; 274 bus-width = <4>; 275 276 marvell,pad-type = "sd"; 277 };