cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra20-sdhci.yaml (9843B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NVIDIA Tegra Secure Digital Host Controller
      8
      9maintainers:
     10  - Thierry Reding <thierry.reding@gmail.com>
     11  - Jon Hunter <jonathanh@nvidia.com>
     12
     13description: |
     14  This controller on Tegra family SoCs provides an interface for MMC, SD, and
     15  SDIO types of memory cards.
     16
     17  This file documents differences between the core properties described by
     18  mmc-controller.yaml and the properties for the Tegra SDHCI controller.
     19
     20properties:
     21  compatible:
     22    oneOf:
     23      - enum:
     24          - nvidia,tegra20-sdhci
     25          - nvidia,tegra30-sdhci
     26          - nvidia,tegra114-sdhci
     27          - nvidia,tegra124-sdhci
     28          - nvidia,tegra210-sdhci
     29          - nvidia,tegra186-sdhci
     30          - nvidia,tegra194-sdhci
     31
     32      - items:
     33          - const: nvidia,tegra132-sdhci
     34          - const: nvidia,tegra124-sdhci
     35
     36      - items:
     37          - enum:
     38              - nvidia,tegra194-sdhci
     39              - nvidia,tegra234-sdhci
     40          - const: nvidia,tegra186-sdhci
     41
     42  reg:
     43    maxItems: 1
     44
     45  interrupts:
     46    maxItems: 1
     47
     48  assigned-clocks: true
     49  assigned-clock-parents: true
     50  assigned-clock-rates: true
     51
     52  clocks:
     53    minItems: 1
     54    maxItems: 2
     55
     56  clock-names:
     57    minItems: 1
     58    maxItems: 2
     59
     60  resets:
     61    items:
     62      - description: module reset
     63
     64  reset-names:
     65    items:
     66      - const: sdhci
     67
     68  power-gpios:
     69    description: specify GPIOs for power control
     70    maxItems: 1
     71
     72  interconnects:
     73    items:
     74      - description: memory read client
     75      - description: memory write client
     76
     77  interconnect-names:
     78    items:
     79      - const: dma-mem # read
     80      - const: write
     81
     82  iommus:
     83    maxItems: 1
     84
     85  operating-points-v2:
     86    $ref: "/schemas/types.yaml#/definitions/phandle"
     87
     88  power-domains:
     89    items:
     90      - description: phandle to the core power domain
     91
     92  nvidia,default-tap:
     93    description: Specify the default inbound sampling clock trimmer value for
     94      non-tunable modes.
     95
     96      The values are used for compensating trace length differences by
     97      adjusting the sampling point. The values are programmed to the Vendor
     98      Clock Control Register. Please refer to the reference manual of the SoC
     99      for correct values.
    100
    101      The DQS trim values are only used on controllers which support HS400
    102      timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
    103    $ref: "/schemas/types.yaml#/definitions/uint32"
    104
    105  nvidia,default-trim:
    106    description: Specify the default outbound clock trimmer value.
    107    $ref: "/schemas/types.yaml#/definitions/uint32"
    108
    109  nvidia,dqs-trim:
    110    description: Specify DQS trim value for HS400 timing.
    111    $ref: "/schemas/types.yaml#/definitions/uint32"
    112
    113  nvidia,pad-autocal-pull-down-offset-1v8:
    114    description: Specify drive strength calibration offsets for 1.8 V
    115      signaling modes.
    116    $ref: "/schemas/types.yaml#/definitions/uint32"
    117
    118  nvidia,pad-autocal-pull-down-offset-1v8-timeout:
    119    description: Specify drive strength used as a fallback in case the
    120      automatic calibration times out on a 1.8 V signaling mode.
    121    $ref: "/schemas/types.yaml#/definitions/uint32"
    122
    123  nvidia,pad-autocal-pull-down-offset-3v3:
    124    description: Specify drive strength calibration offsets for 3.3 V
    125      signaling modes.
    126    $ref: "/schemas/types.yaml#/definitions/uint32"
    127
    128  nvidia,pad-autocal-pull-down-offset-3v3-timeout:
    129    description: Specify drive strength used as a fallback in case the
    130      automatic calibration times out on a 3.3 V signaling mode.
    131    $ref: "/schemas/types.yaml#/definitions/uint32"
    132
    133  nvidia,pad-autocal-pull-down-offset-sdr104:
    134    description: Specify drive strength calibration offsets for SDR104 mode.
    135    $ref: "/schemas/types.yaml#/definitions/uint32"
    136
    137  nvidia,pad-autocal-pull-down-offset-hs400:
    138    description: Specify drive strength calibration offsets for HS400 mode.
    139    $ref: "/schemas/types.yaml#/definitions/uint32"
    140
    141  nvidia,pad-autocal-pull-up-offset-1v8:
    142    description: Specify drive strength calibration offsets for 1.8 V
    143      signaling modes.
    144    $ref: "/schemas/types.yaml#/definitions/uint32"
    145
    146  nvidia,pad-autocal-pull-up-offset-1v8-timeout:
    147    description: Specify drive strength used as a fallback in case the
    148      automatic calibration times out on a 1.8 V signaling mode.
    149    $ref: "/schemas/types.yaml#/definitions/uint32"
    150
    151  nvidia,pad-autocal-pull-up-offset-3v3:
    152    description: Specify drive strength calibration offsets for 3.3 V
    153      signaling modes.
    154
    155      The property values are drive codes which are programmed into the
    156      PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
    157      register. A higher value corresponds to higher drive strength. Please
    158      refer to the reference manual of the SoC for correct values. The SDR104
    159      and HS400 timing specific values are used in corresponding modes if
    160      specified.
    161    $ref: "/schemas/types.yaml#/definitions/uint32"
    162
    163  nvidia,pad-autocal-pull-up-offset-3v3-timeout:
    164    description: Specify drive strength used as a fallback in case the
    165      automatic calibration times out on a 3.3 V signaling mode.
    166    $ref: "/schemas/types.yaml#/definitions/uint32"
    167
    168  nvidia,pad-autocal-pull-up-offset-sdr104:
    169    description: Specify drive strength calibration offsets for SDR104 mode.
    170    $ref: "/schemas/types.yaml#/definitions/uint32"
    171
    172  nvidia,pad-autocal-pull-up-offset-hs400:
    173    description: Specify drive strength calibration offsets for HS400 mode.
    174    $ref: "/schemas/types.yaml#/definitions/uint32"
    175
    176  nvidia,only-1-8v:
    177    description: The presence of this property indicates that the controller
    178      operates at a 1.8 V fixed I/O voltage.
    179    $ref: "/schemas/types.yaml#/definitions/flag"
    180
    181required:
    182  - compatible
    183  - reg
    184  - interrupts
    185  - clocks
    186  - resets
    187  - reset-names
    188
    189allOf:
    190  - $ref: "mmc-controller.yaml"
    191  - if:
    192      properties:
    193        compatible:
    194          contains:
    195            enum:
    196              - nvidia,tegra20-sdhci
    197              - nvidia,tegra30-sdhci
    198              - nvidia,tegra114-sdhci
    199              - nvidia,tegra124-sdhci
    200    then:
    201      properties:
    202        clocks:
    203          items:
    204            - description: module clock
    205    else:
    206      properties:
    207        clocks:
    208          items:
    209            - description: module clock
    210            - description: timeout clock
    211
    212        clock-names:
    213          items:
    214            - const: sdhci
    215            - const: tmclk
    216      required:
    217        - clock-names
    218
    219  - if:
    220      properties:
    221        compatible:
    222          contains:
    223            const: nvidia,tegra210-sdhci
    224    then:
    225      properties:
    226        pinctrl-names:
    227          oneOf:
    228            - items:
    229                - const: sdmmc-3v3
    230                  description: pad configuration for 3.3 V
    231                - const: sdmmc-1v8
    232                  description: pad configuration for 1.8 V
    233                - const: sdmmc-3v3-drv
    234                  description: pull-up/down configuration for 3.3 V
    235                - const: sdmmc-1v8-drv
    236                  description: pull-up/down configuration for 1.8 V
    237            - items:
    238                - const: sdmmc-3v3-drv
    239                  description: pull-up/down configuration for 3.3 V
    240                - const: sdmmc-1v8-drv
    241                  description: pull-up/down configuration for 1.8 V
    242            - items:
    243                - const: sdmmc-1v8-drv
    244                  description: pull-up/down configuration for 1.8 V
    245      required:
    246        - clock-names
    247  - if:
    248      properties:
    249        compatible:
    250          contains:
    251            enum:
    252              - nvidia,tegra186-sdhci
    253              - nvidia,tegra194-sdhci
    254    then:
    255      properties:
    256        pinctrl-names:
    257          items:
    258            - const: sdmmc-3v3
    259              description: pad configuration for 3.3 V
    260            - const: sdmmc-1v8
    261              description: pad configuration for 1.8 V
    262      required:
    263        - clock-names
    264
    265unevaluatedProperties: false
    266
    267examples:
    268  - |
    269    #include <dt-bindings/interrupt-controller/arm-gic.h>
    270
    271    mmc@c8000200 {
    272        compatible = "nvidia,tegra20-sdhci";
    273        reg = <0xc8000200 0x200>;
    274        interrupts = <47>;
    275        clocks = <&tegra_car 14>;
    276        resets = <&tegra_car 14>;
    277        reset-names = "sdhci";
    278        cd-gpios = <&gpio 69 0>; /* gpio PI5 */
    279        wp-gpios = <&gpio 57 0>; /* gpio PH1 */
    280        power-gpios = <&gpio 155 0>; /* gpio PT3 */
    281        bus-width = <8>;
    282    };
    283
    284  - |
    285    #include <dt-bindings/clock/tegra210-car.h>
    286    #include <dt-bindings/interrupt-controller/arm-gic.h>
    287
    288    mmc@700b0000 {
    289        compatible = "nvidia,tegra210-sdhci";
    290        reg = <0x700b0000 0x200>;
    291        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    292        clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
    293                 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
    294        clock-names = "sdhci", "tmclk";
    295        resets = <&tegra_car 14>;
    296        reset-names = "sdhci";
    297        pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
    298                        "sdmmc-3v3-drv", "sdmmc-1v8-drv";
    299        pinctrl-0 = <&sdmmc1_3v3>;
    300        pinctrl-1 = <&sdmmc1_1v8>;
    301        pinctrl-2 = <&sdmmc1_3v3_drv>;
    302        pinctrl-3 = <&sdmmc1_1v8_drv>;
    303        nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
    304        nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
    305        nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
    306        nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
    307        nvidia,default-tap = <0x2>;
    308        nvidia,default-trim = <0x4>;
    309        assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
    310                          <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
    311                          <&tegra_car TEGRA210_CLK_PLL_C4>;
    312        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
    313        assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
    314    };