cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sdhci-atmel.txt (1267B)


      1* Atmel SDHCI controller
      2
      3This file documents the differences between the core properties in
      4Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
      5sdhci-of-at91 driver.
      6
      7Required properties:
      8- compatible:		Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci".
      9- clocks:		Phandlers to the clocks.
     10- clock-names:		Must be "hclock", "multclk", "baseclk" for
     11			"atmel,sama5d2-sdhci".
     12			Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".
     13
     14Optional properties:
     15- assigned-clocks:	The same with "multclk".
     16- assigned-clock-rates	The rate of "multclk" in order to not rely on the
     17			gck configuration set by previous components.
     18- microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
     19  inverted. The default polarity for this signal is described in the datasheet.
     20  For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
     21  and a capacitor (see "SDMMC I/O Calibration" chapter).
     22
     23Example:
     24
     25mmc0: sdio-host@a0000000 {
     26	compatible = "atmel,sama5d2-sdhci";
     27	reg = <0xa0000000 0x300>;
     28	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
     29	clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
     30	clock-names = "hclock", "multclk", "baseclk";
     31	assigned-clocks = <&sdmmc0_gclk>;
     32	assigned-clock-rates = <480000000>;
     33};