sdhci-msm.yaml (5020B)
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Qualcomm SDHCI controller (sdhci-msm) 9 10maintainers: 11 - Bhupesh Sharma <bhupesh.sharma@linaro.org> 12 13description: 14 Secure Digital Host Controller Interface (SDHCI) present on 15 Qualcomm SOCs supports SD/MMC/SDIO devices. 16 17properties: 18 compatible: 19 oneOf: 20 - items: 21 - enum: 22 - qcom,apq8084-sdhci 23 - qcom,msm8226-sdhci 24 - qcom,msm8953-sdhci 25 - qcom,msm8974-sdhci 26 - qcom,msm8916-sdhci 27 - qcom,msm8992-sdhci 28 - qcom,msm8994-sdhci 29 - qcom,msm8996-sdhci 30 - qcom,qcs404-sdhci 31 - qcom,sc7180-sdhci 32 - qcom,sc7280-sdhci 33 - qcom,sdm630-sdhci 34 - qcom,sdm845-sdhci 35 - qcom,sdx55-sdhci 36 - qcom,sdx65-sdhci 37 - qcom,sm6125-sdhci 38 - qcom,sm6350-sdhci 39 - qcom,sm8150-sdhci 40 - qcom,sm8250-sdhci 41 - enum: 42 - qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 43 - qcom,sdhci-msm-v5 # for sdcc version 5.0 44 - items: 45 - const: qcom,sdhci-msm-v4 # Deprecated (only for backward compatibility) 46 # for sdcc versions less than 5.0 47 48 reg: 49 minItems: 1 50 items: 51 - description: Host controller register map 52 - description: SD Core register map 53 - description: CQE register map 54 - description: Inline Crypto Engine register map 55 56 clocks: 57 minItems: 3 58 items: 59 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock 60 - description: SDC MMC clock, MCLK 61 - description: TCXO clock 62 - description: clock for Inline Crypto Engine 63 - description: SDCC bus voter clock 64 - description: reference clock for RCLK delay calibration 65 - description: sleep clock for RCLK delay calibration 66 67 clock-names: 68 minItems: 2 69 items: 70 - const: iface 71 - const: core 72 - const: xo 73 - const: ice 74 - const: bus 75 - const: cal 76 - const: sleep 77 78 interrupts: 79 maxItems: 2 80 81 interrupt-names: 82 items: 83 - const: hc_irq 84 - const: pwr_irq 85 86 pinctrl-names: 87 minItems: 1 88 items: 89 - const: default 90 - const: sleep 91 92 pinctrl-0: 93 description: 94 Should specify pin control groups used for this controller. 95 96 qcom,ddr-config: 97 $ref: /schemas/types.yaml#/definitions/uint32 98 description: platform specific settings for DDR_CONFIG reg. 99 100 qcom,dll-config: 101 $ref: /schemas/types.yaml#/definitions/uint32 102 description: platform specific settings for DLL_CONFIG reg. 103 104 iommus: 105 minItems: 1 106 maxItems: 8 107 description: | 108 phandle to apps_smmu node with sid mask. 109 110 interconnects: 111 items: 112 - description: data path, sdhc to ddr 113 - description: config path, cpu to sdhc 114 115 interconnect-names: 116 items: 117 - const: sdhc-ddr 118 - const: cpu-sdhc 119 120 power-domains: 121 description: A phandle to sdhci power domain node 122 maxItems: 1 123 124patternProperties: 125 '^opp-table(-[a-z0-9]+)?$': 126 if: 127 properties: 128 compatible: 129 const: operating-points-v2 130 then: 131 patternProperties: 132 '^opp-?[0-9]+$': 133 required: 134 - required-opps 135 136required: 137 - compatible 138 - reg 139 - clocks 140 - clock-names 141 - interrupts 142 143additionalProperties: true 144 145examples: 146 - | 147 #include <dt-bindings/interrupt-controller/arm-gic.h> 148 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 149 #include <dt-bindings/clock/qcom,rpmh.h> 150 #include <dt-bindings/power/qcom-rpmpd.h> 151 152 sdhc_2: sdhci@8804000 { 153 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 154 reg = <0 0x08804000 0 0x1000>; 155 156 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "hc_irq", "pwr_irq"; 159 160 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 161 <&gcc GCC_SDCC2_APPS_CLK>, 162 <&rpmhcc RPMH_CXO_CLK>; 163 clock-names = "iface", "core", "xo"; 164 iommus = <&apps_smmu 0x4a0 0x0>; 165 qcom,dll-config = <0x0007642c>; 166 qcom,ddr-config = <0x80040868>; 167 power-domains = <&rpmhpd SM8250_CX>; 168 169 operating-points-v2 = <&sdhc2_opp_table>; 170 171 sdhc2_opp_table: opp-table { 172 compatible = "operating-points-v2"; 173 174 opp-19200000 { 175 opp-hz = /bits/ 64 <19200000>; 176 required-opps = <&rpmhpd_opp_min_svs>; 177 }; 178 179 opp-50000000 { 180 opp-hz = /bits/ 64 <50000000>; 181 required-opps = <&rpmhpd_opp_low_svs>; 182 }; 183 184 opp-100000000 { 185 opp-hz = /bits/ 64 <100000000>; 186 required-opps = <&rpmhpd_opp_svs>; 187 }; 188 189 opp-202000000 { 190 opp-hz = /bits/ 64 <202000000>; 191 required-opps = <&rpmhpd_opp_svs_l1>; 192 }; 193 }; 194 };