cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sdhci-sprd.txt (2709B)

      1* Spreadtrum SDHCI controller (sdhci-sprd)
      2
      3The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
      4for MMC, SD and SDIO types of cards.
      5
      6This file documents differences between the core properties in mmc.txt
      7and the properties used by the sdhci-sprd driver.
      8
      9Required properties:
     10- compatible: Should contain "sprd,sdhci-r11".
     11- reg: physical base address of the controller and length.
     12- interrupts: Interrupts used by the SDHCI controller.
     13- clocks: Should contain phandle for the clock feeding the SDHCI controller
     14- clock-names: Should contain the following:
     15	"sdio" - SDIO source clock (required)
     16	"enable" - gate clock which used for enabling/disabling the device (required)
     17	"2x_enable" - gate clock controlling the device for some special platforms (optional)
     18
     19Optional properties:
     20- assigned-clocks: the same with "sdio" clock
     21- assigned-clock-parents: the default parent of "sdio" clock
     22- pinctrl-names: should be "default", "state_uhs"
     23- pinctrl-0: should contain default/high speed pin control
     24- pinctrl-1: should contain uhs mode pin control
     25
     26PHY DLL delays are used to delay the data valid window, and align the window
     27to sampling clock. PHY DLL delays can be configured by following properties,
     28and each property contains 4 cells which are used to configure the clock data
     29write line delay value, clock read command line delay value, clock read data
     30positive edge delay value and clock read data negative edge delay value.
     31Each cell's delay value unit is cycle of the PHY clock.
     32
     33- sprd,phy-delay-legacy: Delay value for legacy timing.
     34- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
     35- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
     36- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
     37- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
     38- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
     39- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
     40- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
     41- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
     42
     43Examples:
     44
     45sdio0: sdio@20600000 {
     46	compatible  = "sprd,sdhci-r11";
     47	reg = <0 0x20600000 0 0x1000>;
     48	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
     49
     50	clock-names = "sdio", "enable";
     51	clocks = <&ap_clk CLK_EMMC_2X>,
     52		 <&apahb_gate CLK_EMMC_EB>;
     53	assigned-clocks = <&ap_clk CLK_EMMC_2X>;
     54	assigned-clock-parents = <&rpll CLK_RPLL_390M>;
     55
     56	pinctrl-names = "default", "state_uhs";
     57	pinctrl-0 = <&sd0_pins_default>;
     58	pinctrl-1 = <&sd0_pins_uhs>;
     59
     60	sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
     61	bus-width = <8>;
     62	non-removable;
     63	no-sdio;
     64	no-sd;
     65	cap-mmc-hw-reset;
     66	status = "okay";
     67};