cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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usdhi6rol0.txt (1161B)


      1* Renesas usdhi6rol0 SD/SDIO host controller
      2
      3Required properties:
      4
      5- compatible:	must be
      6		"renesas,usdhi6rol0"
      7- interrupts:	3 interrupts, named "card detect", "data" and "SDIO" must be
      8		specified
      9- clocks:	a clock binding for the IMCLK input
     10
     11Optional properties:
     12
     13- vmmc-supply:	a phandle of a regulator, supplying Vcc to the card
     14- vqmmc-supply:	a phandle of a regulator, supplying VccQ to the card
     15- pinctrl-names: Can contain a "default" entry and a "state_uhs"
     16                 entry. The state_uhs entry is used together with the default
     17                 entry when the board requires distinct settings for UHS speeds.
     18
     19- pinctrl-N: One property for each name listed in pinctrl-names, see
     20             ../pinctrl/pinctrl-bindings.txt.
     21
     22Additionally any standard mmc bindings from mmc.txt can be used.
     23
     24Example:
     25
     26sd0: sd@ab000000 {
     27	compatible = "renesas,usdhi6rol0";
     28	reg = <0xab000000 0x200>;
     29	interrupts = <0 23 0x4
     30		      0 24 0x4
     31		      0 25 0x4>;
     32	interrupt-names = "card detect", "data", "SDIO";
     33	bus-width = <4>;
     34	max-frequency = <50000000>;
     35	cap-power-off-card;
     36	clocks = <&imclk>;
     37	vmmc-supply = <&vcc_sd0>;
     38	vqmmc-supply = <&vccq_sd0>;
     39};