cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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arasan,nand-controller.yaml (1264B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Arasan NAND Flash Controller with ONFI 3.1 support device tree bindings
      8
      9allOf:
     10  - $ref: "nand-controller.yaml"
     11
     12maintainers:
     13  - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
     14
     15properties:
     16  compatible:
     17    items:
     18      - enum:
     19          - xlnx,zynqmp-nand-controller
     20      - const: arasan,nfc-v3p10
     21
     22  reg:
     23    maxItems: 1
     24
     25  clocks:
     26    items:
     27      - description: Controller clock
     28      - description: NAND bus clock
     29
     30  clock-names:
     31    items:
     32      - const: controller
     33      - const: bus
     34
     35  interrupts:
     36    maxItems: 1
     37
     38  "#address-cells": true
     39  "#size-cells": true
     40
     41required:
     42  - compatible
     43  - reg
     44  - clocks
     45  - clock-names
     46  - interrupts
     47
     48additionalProperties: true
     49
     50examples:
     51  - |
     52    nfc: nand-controller@ff100000 {
     53        compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
     54        reg = <0xff100000 0x1000>;
     55        clock-names = "controller", "bus";
     56        clocks = <&clk200>, <&clk100>;
     57        interrupt-parent = <&gic>;
     58        interrupts = <0 14 4>;
     59        #address-cells = <1>;
     60        #size-cells = <0>;
     61    };