brcm,brcmnand.yaml (7276B)
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom STB NAND Controller 8 9maintainers: 10 - Brian Norris <computersforpeace@gmail.com> 11 - Kamal Dasu <kdasu.kdev@gmail.com> 12 13description: | 14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND 15 flash chips. It has a memory-mapped register interface for both control 16 registers and for its data input/output buffer. On some SoCs, this controller 17 is paired with a custom DMA engine (inventively named "Flash DMA") which 18 supports basic PROGRAM and READ functions, among other features. 19 20 This controller was originally designed for STB SoCs (BCM7xxx) but is now 21 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and 22 iProc/Cygnus. Its history includes several similar (but not fully register 23 compatible) versions. 24 25 -- Additional SoC-specific NAND controller properties -- 26 27 The NAND controller is integrated differently on the variety of SoCs on which 28 it is found. Part of this integration involves providing status and enable 29 bits with which to control the 8 exposed NAND interrupts, as well as hardware 30 for configuring the endianness of the data bus. On some SoCs, these features 31 are handled via standard, modular components (e.g., their interrupts look like 32 a normal IRQ chip), but on others, they are controlled in unique and 33 interesting ways, sometimes with registers that lump multiple NAND-related 34 functions together. The former case can be described simply by the standard 35 interrupts properties in the main controller node. But for the latter 36 exceptional cases, we define additional 'compatible' properties and associated 37 register resources within the NAND controller node above. 38 39properties: 40 compatible: 41 oneOf: 42 - items: 43 - enum: 44 - brcm,brcmnand-v2.1 45 - brcm,brcmnand-v2.2 46 - brcm,brcmnand-v4.0 47 - brcm,brcmnand-v5.0 48 - brcm,brcmnand-v6.0 49 - brcm,brcmnand-v6.1 50 - brcm,brcmnand-v6.2 51 - brcm,brcmnand-v7.0 52 - brcm,brcmnand-v7.1 53 - brcm,brcmnand-v7.2 54 - brcm,brcmnand-v7.3 55 - const: brcm,brcmnand 56 - description: BCM63138 SoC-specific NAND controller 57 items: 58 - const: brcm,nand-bcm63138 59 - enum: 60 - brcm,brcmnand-v7.0 61 - brcm,brcmnand-v7.1 62 - const: brcm,brcmnand 63 - description: iProc SoC-specific NAND controller 64 items: 65 - const: brcm,nand-iproc 66 - const: brcm,brcmnand-v6.1 67 - const: brcm,brcmnand 68 - description: BCM63168 SoC-specific NAND controller 69 items: 70 - const: brcm,nand-bcm63168 71 - const: brcm,nand-bcm6368 72 - const: brcm,brcmnand-v4.0 73 - const: brcm,brcmnand 74 75 reg: 76 minItems: 1 77 maxItems: 6 78 79 reg-names: 80 minItems: 1 81 maxItems: 6 82 items: 83 enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ] 84 85 interrupts: 86 minItems: 1 87 items: 88 - description: NAND CTLRDY interrupt 89 - description: FLASH_DMA_DONE if flash DMA is available 90 - description: FLASH_EDU_DONE if EDU is available 91 92 interrupt-names: 93 minItems: 1 94 items: 95 - const: nand_ctlrdy 96 - const: flash_dma_done 97 - const: flash_edu_done 98 99 clocks: 100 maxItems: 1 101 description: reference to the clock for the NAND controller 102 103 clock-names: 104 const: nand 105 106 brcm,nand-has-wp: 107 description: > 108 Some versions of this IP include a write-protect 109 (WP) control bit. It is always available on >= 110 v7.0. Use this property to describe the rare 111 earlier versions of this core that include WP 112 type: boolean 113 114patternProperties: 115 "^nand@[a-f0-9]$": 116 type: object 117 properties: 118 compatible: 119 const: brcm,nandcs 120 121 nand-ecc-step-size: 122 enum: [ 512, 1024 ] 123 124 brcm,nand-oob-sector-size: 125 description: | 126 integer, to denote the spare area sector size 127 expected for the ECC layout in use. This size, in 128 addition to the strength and step-size, 129 determines how the hardware BCH engine will lay 130 out the parity bytes it stores on the flash. 131 This property can be automatically determined by 132 the flash geometry (particularly the NAND page 133 and OOB size) in many cases, but when booting 134 from NAND, the boot controller has only a limited 135 number of available options for its default ECC 136 layout. 137 $ref: /schemas/types.yaml#/definitions/uint32 138 139allOf: 140 - $ref: nand-controller.yaml# 141 - if: 142 properties: 143 compatible: 144 contains: 145 const: brcm,nand-bcm63138 146 then: 147 properties: 148 reg-names: 149 items: 150 - const: nand 151 - const: nand-int-base 152 - if: 153 properties: 154 compatible: 155 contains: 156 const: brcm,nand-bcm6368 157 then: 158 properties: 159 reg-names: 160 items: 161 - const: nand 162 - const: nand-int-base 163 - const: nand-cache 164 - if: 165 properties: 166 compatible: 167 contains: 168 const: brcm,nand-iproc 169 then: 170 properties: 171 reg-names: 172 items: 173 - const: nand 174 - const: iproc-idm 175 - const: iproc-ext 176 177unevaluatedProperties: false 178 179required: 180 - reg 181 - reg-names 182 - interrupts 183 184examples: 185 - | 186 nand-controller@f0442800 { 187 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; 188 reg = <0xf0442800 0x600>, 189 <0xf0443000 0x100>; 190 reg-names = "nand", "flash-dma"; 191 interrupt-parent = <&hif_intr2_intc>; 192 interrupts = <24>, <4>; 193 194 #address-cells = <1>; 195 #size-cells = <0>; 196 197 nand@1 { 198 compatible = "brcm,nandcs"; 199 reg = <1>; // Chip select 1 200 nand-on-flash-bbt; 201 nand-ecc-strength = <12>; 202 nand-ecc-step-size = <512>; 203 204 #address-cells = <1>; 205 #size-cells = <1>; 206 }; 207 }; 208 - | 209 nand-controller@10000200 { 210 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", 211 "brcm,brcmnand-v4.0", "brcm,brcmnand"; 212 reg = <0x10000200 0x180>, 213 <0x100000b0 0x10>, 214 <0x10000600 0x200>; 215 reg-names = "nand", "nand-int-base", "nand-cache"; 216 interrupt-parent = <&periph_intc>; 217 interrupts = <50>; 218 clocks = <&periph_clk 20>; 219 clock-names = "nand"; 220 221 #address-cells = <1>; 222 #size-cells = <0>; 223 224 nand@0 { 225 compatible = "brcm,nandcs"; 226 reg = <0>; 227 nand-on-flash-bbt; 228 nand-ecc-strength = <1>; 229 nand-ecc-step-size = <512>; 230 231 #address-cells = <1>; 232 #size-cells = <1>; 233 }; 234 };