cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel,lgm-nand.yaml (1774B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Intel LGM SoC NAND Controller Device Tree Bindings
      8
      9allOf:
     10  - $ref: "nand-controller.yaml"
     11
     12maintainers:
     13  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
     14
     15properties:
     16  compatible:
     17    const: intel,lgm-nand
     18
     19  reg:
     20    maxItems: 6
     21
     22  reg-names:
     23    items:
     24      - const: ebunand
     25      - const: hsnand
     26      - const: nand_cs0
     27      - const: nand_cs1
     28      - const: addr_sel0
     29      - const: addr_sel1
     30
     31  clocks:
     32    maxItems: 1
     33
     34  dmas:
     35    maxItems: 2
     36
     37  dma-names:
     38    items:
     39      - const: tx
     40      - const: rx
     41
     42  "#address-cells":
     43    const: 1
     44
     45  "#size-cells":
     46    const: 0
     47
     48patternProperties:
     49  "^nand@[a-f0-9]+$":
     50    type: object
     51    properties:
     52      reg:
     53        minimum: 0
     54        maximum: 7
     55
     56      nand-ecc-mode: true
     57
     58      nand-ecc-algo:
     59        const: hw
     60
     61    additionalProperties: false
     62
     63required:
     64  - compatible
     65  - reg
     66  - reg-names
     67  - clocks
     68  - dmas
     69  - dma-names
     70  - "#address-cells"
     71  - "#size-cells"
     72
     73additionalProperties: false
     74
     75examples:
     76  - |
     77    nand-controller@e0f00000 {
     78      compatible = "intel,lgm-nand";
     79      reg = <0xe0f00000 0x100>,
     80            <0xe1000000 0x300>,
     81            <0xe1400000 0x8000>,
     82            <0xe1c00000 0x1000>,
     83            <0x17400000 0x4>,
     84            <0x17c00000 0x4>;
     85      reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
     86        "addr_sel0", "addr_sel1";
     87      clocks = <&cgu0 125>;
     88      dmas = <&dma0 8>, <&dma0 9>;
     89      dma-names = "tx", "rx";
     90      #address-cells = <1>;
     91      #size-cells = <0>;
     92
     93      nand@0 {
     94        reg = <0>;
     95        nand-ecc-mode = "hw";
     96      };
     97    };
     98
     99...