cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell-nand.txt (4584B)

      1Marvell NAND Flash Controller (NFC)
      2
      3Required properties:
      4- compatible: can be one of the following:
      5    * "marvell,armada-8k-nand-controller"
      6    * "marvell,armada370-nand-controller"
      7    * "marvell,pxa3xx-nand-controller"
      8    * "marvell,armada-8k-nand" (deprecated)
      9    * "marvell,armada370-nand" (deprecated)
     10    * "marvell,pxa3xx-nand" (deprecated)
     11  Compatibles marked deprecated support only the old bindings described
     12  at the bottom.
     13- reg: NAND flash controller memory area.
     14- #address-cells: shall be set to 1. Encode the NAND CS.
     15- #size-cells: shall be set to 0.
     16- interrupts: shall define the NAND controller interrupt.
     17- clocks: shall reference the NAND controller clocks, the second one is
     18  is only needed for the Armada 7K/8K SoCs
     19- clock-names: mandatory if there is a second clock, in this case there
     20  should be one clock named "core" and another one named "reg"
     21- marvell,system-controller: Set to retrieve the syscon node that handles
     22  NAND controller related registers (only required with the
     23  "marvell,armada-8k-nand[-controller]" compatibles).
     24
     25Optional properties:
     26- label: see partition.txt. New platforms shall omit this property.
     27- dmas: shall reference DMA channel associated to the NAND controller.
     28  This property is only used with "marvell,pxa3xx-nand[-controller]"
     29  compatible strings.
     30- dma-names: shall be "rxtx".
     31  This property is only used with "marvell,pxa3xx-nand[-controller]"
     32  compatible strings.
     33
     34Optional children nodes:
     35Children nodes represent the available NAND chips.
     36
     37Required properties:
     38- reg: shall contain the native Chip Select ids (0-3).
     39- nand-rb: see nand-controller.yaml (0-1).
     40
     41Optional properties:
     42- marvell,nand-keep-config: orders the driver not to take the timings
     43  from the core and leaving them completely untouched. Bootloader
     44  timings will then be used.
     45- label: MTD name.
     46- nand-on-flash-bbt: see nand-controller.yaml.
     47- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
     48- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
     49  not using hardware ECC. Howerver, it may be added when using hardware
     50  ECC for clarification but will be ignored by the driver because ECC
     51  mode is chosen depending on the page size and the strength required by
     52  the NAND chip. This value may be overwritten with nand-ecc-strength
     53  property.
     54- nand-ecc-strength: see nand-controller.yaml.
     55- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
     56  use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
     57  step size will shrink or grow in order to fit the required strength.
     58  Step sizes are not completely random for all and follow certain
     59  patterns described in AN-379, "Marvell SoC NFC ECC".
     60
     61See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
     62generic bindings.
     63
     64
     65Example:
     66nand_controller: nand-controller@d0000 {
     67	compatible = "marvell,armada370-nand-controller";
     68	reg = <0xd0000 0x54>;
     69	#address-cells = <1>;
     70	#size-cells = <0>;
     71	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
     72	clocks = <&coredivclk 0>;
     73
     74	nand@0 {
     75		reg = <0>;
     76		label = "main-storage";
     77		nand-rb = <0>;
     78		nand-ecc-mode = "hw";
     79		marvell,nand-keep-config;
     80		nand-on-flash-bbt;
     81		nand-ecc-strength = <4>;
     82		nand-ecc-step-size = <512>;
     83
     84		partitions {
     85			compatible = "fixed-partitions";
     86			#address-cells = <1>;
     87			#size-cells = <1>;
     88
     89			partition@0 {
     90				label = "Rootfs";
     91				reg = <0x00000000 0x40000000>;
     92			};
     93		};
     94	};
     95};
     96
     97
     98Note on legacy bindings: One can find, in not-updated device trees,
     99bindings slightly different than described above with other properties
    100described below as well as the partitions node at the root of a so
    101called "nand" node (without clear controller/chip separation).
    102
    103Legacy properties:
    104- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
    105  used it, this bit was set by the bootloader for many boards and even if
    106  it is marked reserved in several datasheets, it might be needed to set
    107  it (otherwise it is harmless) so whether or not this property is set,
    108  the bit is selected by the driver.
    109- num-cs: Number of chip-select lines to use, all boards blindly set 1
    110  to this and for a reason, other values would have failed. The value of
    111  this property is ignored.
    112
    113Example:
    114
    115	nand0: nand@43100000 {
    116		compatible = "marvell,pxa3xx-nand";
    117		reg = <0x43100000 90>;
    118		interrupts = <45>;
    119		dmas = <&pdma 97 0>;
    120		dma-names = "rxtx";
    121		#address-cells = <1>;
    122		marvell,nand-keep-config;
    123		marvell,nand-enable-arbiter;
    124		num-cs = <1>;
    125		/* Partitions (optional) */
    126       };