cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mxic-nand.txt (1094B)

      1Macronix Raw NAND Controller Device Tree Bindings
      2-------------------------------------------------
      3
      4Required properties:
      5- compatible: should be "mxic,multi-itfc-v009-nand-controller"
      6- reg: should contain 1 entry for the registers
      7- #address-cells: should be set to 1
      8- #size-cells: should be set to 0
      9- interrupts: interrupt line connected to this raw NAND controller
     10- clock-names: should contain "ps", "send" and "send_dly"
     11- clocks: should contain 3 phandles for the "ps", "send" and
     12	 "send_dly" clocks
     13
     14Children nodes:
     15- children nodes represent the available NAND chips.
     16
     17See Documentation/devicetree/bindings/mtd/nand-controller.yaml
     18for more details on generic bindings.
     19
     20Example:
     21
     22	nand: nand-controller@43c30000 {
     23		compatible = "mxic,multi-itfc-v009-nand-controller";
     24		reg = <0x43c30000 0x10000>;
     25		#address-cells = <1>;
     26		#size-cells = <0>;
     27		interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>;
     28		clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
     29		clock-names = "send", "send_dly", "ps";
     30
     31		nand@0 {
     32			reg = <0>;
     33			nand-ecc-mode = "soft";
     34			nand-ecc-algo = "bch";
     35		};
     36	};