cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mxicy,nand-ecc-engine.yaml (1903B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Macronix NAND ECC engine device tree bindings
      8
      9maintainers:
     10  - Miquel Raynal <miquel.raynal@bootlin.com>
     11
     12properties:
     13  compatible:
     14    const: mxicy,nand-ecc-engine-rev3
     15
     16  reg:
     17    maxItems: 1
     18
     19  clocks:
     20    maxItems: 1
     21
     22  interrupts:
     23    maxItems: 1
     24
     25required:
     26  - compatible
     27  - reg
     28
     29additionalProperties: false
     30
     31examples:
     32  - |
     33    /* External configuration */
     34    spi_controller0: spi@43c30000 {
     35        compatible = "mxicy,mx25f0a-spi";
     36        reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
     37        reg-names = "regs", "dirmap";
     38        clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
     39        clock-names = "send_clk", "send_dly_clk", "ps_clk";
     40        #address-cells = <1>;
     41        #size-cells = <0>;
     42
     43        flash@0 {
     44            compatible = "spi-nand";
     45            reg = <0>;
     46            nand-ecc-engine = <&ecc_engine0>;
     47        };
     48    };
     49
     50    ecc_engine0: ecc@43c40000 {
     51        compatible = "mxicy,nand-ecc-engine-rev3";
     52        reg = <0x43c40000 0x10000>;
     53    };
     54
     55  - |
     56    /* Pipelined configuration */
     57    spi_controller1: spi@43c30000 {
     58        compatible = "mxicy,mx25f0a-spi";
     59        reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
     60        reg-names = "regs", "dirmap";
     61        clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
     62        clock-names = "send_clk", "send_dly_clk", "ps_clk";
     63        #address-cells = <1>;
     64        #size-cells = <0>;
     65        nand-ecc-engine = <&ecc_engine1>;
     66
     67        flash@0 {
     68            compatible = "spi-nand";
     69            reg = <0>;
     70            nand-ecc-engine = <&spi_controller1>;
     71        };
     72    };
     73
     74    ecc_engine1: ecc@43c40000 {
     75        compatible = "mxicy,nand-ecc-engine-rev3";
     76        reg = <0x43c40000 0x10000>;
     77    };