cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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orion-nand.txt (1123B)


      1NAND support for Marvell Orion SoC platforms
      2
      3Required properties:
      4- compatible : "marvell,orion-nand".
      5- reg : Base physical address of the NAND and length of memory mapped
      6	region
      7
      8Optional properties:
      9- cle : Address line number connected to CLE. Default is 0
     10- ale : Address line number connected to ALE. Default is 1
     11- bank-width : Width in bytes of the device. Default is 1
     12- chip-delay : Chip dependent delay for transferring data from array to read
     13               registers in usecs
     14
     15The device tree may optionally contain sub-nodes describing partitions of the
     16address space. See partition.txt for more detail.
     17
     18Example:
     19
     20nand@f4000000 {
     21	#address-cells = <1>;
     22	#size-cells = <1>;
     23	cle = <0>;
     24	ale = <1>;
     25	bank-width = <1>;
     26	chip-delay = <25>;
     27	compatible = "marvell,orion-nand";
     28	reg = <0xf4000000 0x400>;
     29
     30	partition@0 {
     31		label = "u-boot";
     32		reg = <0x0000000 0x100000>;
     33		read-only;
     34	};
     35
     36	partition@100000 {
     37		label = "uImage";
     38		reg = <0x0100000 0x200000>;
     39	};
     40
     41	partition@300000 {
     42		label = "dtb";
     43		reg = <0x0300000 0x100000>;
     44	};
     45
     46	partition@400000 {
     47		label = "root";
     48		reg = <0x0400000 0x7d00000>;
     49	};
     50};