cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas-nandc.yaml (1447B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mtd/renesas-nandc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Renesas R-Car Gen3 & RZ/N1x NAND flash controller device tree bindings
      8
      9maintainers:
     10  - Miquel Raynal <miquel.raynal@bootlin.com>
     11
     12allOf:
     13  - $ref: "nand-controller.yaml"
     14
     15properties:
     16  compatible:
     17    oneOf:
     18      - items:
     19          - enum:
     20              - renesas,r9a06g032-nandc
     21          - const: renesas,rzn1-nandc
     22
     23  reg:
     24    maxItems: 1
     25
     26  interrupts:
     27    maxItems: 1
     28
     29  clocks:
     30    items:
     31      - description: APB host controller clock
     32      - description: External NAND bus clock
     33
     34  clock-names:
     35    items:
     36      - const: hclk
     37      - const: eclk
     38
     39  power-domains:
     40    maxItems: 1
     41
     42required:
     43  - compatible
     44  - reg
     45  - clocks
     46  - clock-names
     47  - power-domains
     48  - interrupts
     49
     50unevaluatedProperties: false
     51
     52examples:
     53  - |
     54    #include <dt-bindings/interrupt-controller/arm-gic.h>
     55    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
     56
     57    nand-controller@40102000 {
     58        compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
     59        reg = <0x40102000 0x2000>;
     60        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
     61        clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
     62        clock-names = "hclk", "eclk";
     63        power-domains = <&sysctrl>;
     64        #address-cells = <1>;
     65        #size-cells = <0>;
     66    };