cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rockchip,nand-controller.yaml (3715B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Rockchip SoCs NAND FLASH Controller (NFC)
      8
      9allOf:
     10  - $ref: "nand-controller.yaml#"
     11
     12maintainers:
     13  - Heiko Stuebner <heiko@sntech.de>
     14
     15properties:
     16  compatible:
     17    oneOf:
     18      - const: rockchip,px30-nfc
     19      - const: rockchip,rk2928-nfc
     20      - const: rockchip,rv1108-nfc
     21      - items:
     22          - const: rockchip,rk3036-nfc
     23          - const: rockchip,rk2928-nfc
     24      - items:
     25          - const: rockchip,rk3308-nfc
     26          - const: rockchip,rv1108-nfc
     27
     28  reg:
     29    maxItems: 1
     30
     31  interrupts:
     32    maxItems: 1
     33
     34  clocks:
     35    minItems: 1
     36    items:
     37      - description: Bus Clock
     38      - description: Module Clock
     39
     40  clock-names:
     41    minItems: 1
     42    items:
     43      - const: ahb
     44      - const: nfc
     45
     46  assigned-clocks:
     47    maxItems: 1
     48
     49  assigned-clock-rates:
     50    maxItems: 1
     51
     52  power-domains:
     53    maxItems: 1
     54
     55patternProperties:
     56  "^nand@[0-7]$":
     57    type: object
     58    properties:
     59      reg:
     60        minimum: 0
     61        maximum: 7
     62
     63      nand-ecc-mode:
     64        const: hw
     65
     66      nand-ecc-step-size:
     67        const: 1024
     68
     69      nand-ecc-strength:
     70        enum: [16, 24, 40, 60, 70]
     71        description: |
     72          The ECC configurations that can be supported are as follows.
     73            NFC v600 ECC 16, 24, 40, 60
     74              RK2928, RK3066, RK3188
     75
     76            NFC v622 ECC 16, 24, 40, 60
     77              RK3036, RK3128
     78
     79            NFC v800 ECC 16
     80              RK3308, RV1108
     81
     82            NFC v900 ECC 16, 40, 60, 70
     83              RK3326, PX30
     84
     85      nand-bus-width:
     86        const: 8
     87
     88      rockchip,boot-blks:
     89        $ref: /schemas/types.yaml#/definitions/uint32
     90        minimum: 2
     91        default: 16
     92        description:
     93          The NFC driver need this information to select ECC
     94          algorithms supported by the boot ROM.
     95          Only used in combination with 'nand-is-boot-medium'.
     96
     97      rockchip,boot-ecc-strength:
     98        enum: [16, 24, 40, 60, 70]
     99        $ref: /schemas/types.yaml#/definitions/uint32
    100        description: |
    101          If specified it indicates that a different BCH/ECC setting is
    102          supported by the boot ROM.
    103            NFC v600 ECC 16, 24
    104              RK2928, RK3066, RK3188
    105
    106            NFC v622 ECC 16, 24, 40, 60
    107              RK3036, RK3128
    108
    109            NFC v800 ECC 16
    110              RK3308, RV1108
    111
    112            NFC v900 ECC 16, 70
    113              RK3326, PX30
    114
    115          Only used in combination with 'nand-is-boot-medium'.
    116
    117required:
    118  - compatible
    119  - reg
    120  - interrupts
    121  - clocks
    122  - clock-names
    123
    124unevaluatedProperties: false
    125
    126examples:
    127  - |
    128    #include <dt-bindings/clock/rk3308-cru.h>
    129    #include <dt-bindings/interrupt-controller/arm-gic.h>
    130    nfc: nand-controller@ff4b0000 {
    131      compatible = "rockchip,rk3308-nfc",
    132                   "rockchip,rv1108-nfc";
    133      reg = <0xff4b0000 0x4000>;
    134      interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
    135      clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
    136      clock-names = "ahb", "nfc";
    137      assigned-clocks = <&clks SCLK_NANDC>;
    138      assigned-clock-rates = <150000000>;
    139
    140      pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
    141                   &flash_rdn &flash_rdy &flash_wrn>;
    142      pinctrl-names = "default";
    143
    144      #address-cells = <1>;
    145      #size-cells = <0>;
    146
    147      nand@0 {
    148        reg = <0>;
    149        label = "rk-nand";
    150        nand-bus-width = <8>;
    151        nand-ecc-mode = "hw";
    152        nand-ecc-step-size = <1024>;
    153        nand-ecc-strength = <16>;
    154        nand-is-boot-medium;
    155        rockchip,boot-blks = <8>;
    156        rockchip,boot-ecc-strength = <16>;
    157      };
    158    };
    159
    160...