cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cavium-mix.txt (1203B)


      1* MIX Ethernet controller.
      2
      3Properties:
      4- compatible: "cavium,octeon-5750-mix"
      5
      6  Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX
      7  devices.
      8
      9- reg: The base addresses of four separate register banks.  The first
     10  bank contains the MIX registers.  The second bank the corresponding
     11  AGL registers.  The third bank are the AGL registers shared by all
     12  MIX devices present.  The fourth bank is the AGL_PRT_CTL shared by
     13  all MIX devices present.
     14
     15- cell-index: A single cell specifying which portion of the shared
     16  register banks corresponds to this MIX device.
     17
     18- interrupts: Two interrupt specifiers.  The first is the MIX
     19  interrupt routing and the second the routing for the AGL interrupts.
     20
     21- phy-handle: Optional, see ethernet.txt file in the same directory.
     22
     23Example:
     24	ethernet@1070000100800 {
     25		compatible = "cavium,octeon-5750-mix";
     26		reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
     27		      <0x11800 0xE0000800 0x0 0x300>, /* AGL */
     28		      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
     29		      <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
     30		cell-index = <1>;
     31		interrupts = <1 18>, < 1 46>;
     32		local-mac-address = [ 00 0f b7 10 63 54 ];
     33		phy-handle = <&phy1>;
     34	};