cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpsw-phy-sel.txt (862B)

      1TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
      2-----------------------------------------------
      3
      4Required properties:
      5- compatible		: Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
      6			  "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
      7			  "ti,am43xx-cpsw-phy-sel" for am43xx platform
      8- reg			: physical base address and size of the cpsw
      9			  registers map
     10- reg-names		: names of the register map given in "reg" node
     11
     12Optional properties:
     13-rmii-clock-ext		: If present, the driver will configure the RMII
     14			  interface to external clock usage
     15
     16Examples:
     17
     18	phy_sel: cpsw-phy-sel@44e10650 {
     19		compatible = "ti,am3352-cpsw-phy-sel";
     20		reg= <0x44e10650 0x4>;
     21		reg-names = "gmii-sel";
     22	};
     23
     24(or)
     25	phy_sel: cpsw-phy-sel@44e10650 {
     26		compatible = "ti,am3352-cpsw-phy-sel";
     27		reg= <0x44e10650 0x4>;
     28		reg-names = "gmii-sel";
     29		rmii-clock-ext;
     30	};