cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpsw.txt (4421B)


      1TI SoC Ethernet Switch Controller Device Tree Bindings
      2------------------------------------------------------
      3
      4Required properties:
      5- compatible		: Should be one of the below:-
      6			  "ti,cpsw" for backward compatible
      7			  "ti,am335x-cpsw" for AM335x controllers
      8			  "ti,am4372-cpsw" for AM437x controllers
      9			  "ti,dra7-cpsw" for DRA7x controllers
     10- reg			: physical base address and size of the cpsw
     11			  registers map
     12- interrupts		: property with a value describing the interrupt
     13			  number
     14- cpdma_channels 	: Specifies number of channels in CPDMA
     15- ale_entries		: Specifies No of entries ALE can hold
     16- bd_ram_size		: Specifies internal descriptor RAM size
     17- mac_control		: Specifies Default MAC control register content
     18			  for the specific platform
     19- slaves		: Specifies number for slaves
     20- active_slave		: Specifies the slave to use for time stamping,
     21			  ethtool and SIOCGMIIPHY
     22- cpsw-phy-sel		: Specifies the phandle to the CPSW phy mode selection
     23			  device. See also cpsw-phy-sel.txt for it's binding.
     24			  Note that in legacy cases cpsw-phy-sel may be
     25			  a child device instead of a phandle
     26			  (DEPRECATED, use phys property instead).
     27
     28Optional properties:
     29- ti,hwmods		: Must be "cpgmac0"
     30- dual_emac		: Specifies Switch to act as Dual EMAC
     31- syscon		: Phandle to the system control device node, which is
     32			  the control module device of the am33x
     33- mode-gpios		: Should be added if one/multiple gpio lines are
     34			  required to be driven so that cpsw data lines
     35			  can be connected to the phy via selective mux.
     36			  For example in dra72x-evm, pcf gpio has to be
     37			  driven low so that cpsw slave 0 and phy data
     38			  lines are connected via mux.
     39- cpts_clock_mult	: Numerator to convert input clock ticks into nanoseconds
     40- cpts_clock_shift	: Denominator to convert input clock ticks into nanoseconds
     41			  Mult and shift will be calculated basing on CPTS
     42			  rftclk frequency if both cpts_clock_shift and
     43			  cpts_clock_mult properties are not provided.
     44
     45Slave Properties:
     46Required properties:
     47- phy-mode		: See ethernet.txt file in the same directory
     48- phys			: phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)
     49
     50Optional properties:
     51- dual_emac_res_vlan	: Specifies VID to be used to segregate the ports
     52- phy_id		: Specifies slave phy id (deprecated, use phy-handle)
     53- phy-handle		: See ethernet.txt file in the same directory
     54
     55The MAC address will be determined using the optional properties
     56defined in ethernet.txt.
     57
     58Slave sub-nodes:
     59- fixed-link		: See fixed-link.txt file in the same directory
     60
     61Note: Exactly one of phy_id, phy-handle, or fixed-link must be specified.
     62
     63Note: "ti,hwmods" field is used to fetch the base address and irq
     64resources from TI, omap hwmod data base during device registration.
     65Future plan is to migrate hwmod data base contents into device tree
     66blob so that, all the required data will be used from device tree dts
     67file.
     68
     69Examples:
     70
     71	mac: ethernet@4a100000 {
     72		compatible = "ti,cpsw";
     73		reg = <0x4A100000 0x1000>;
     74		interrupts = <55 0x4>;
     75		interrupt-parent = <&intc>;
     76		cpdma_channels = <8>;
     77		ale_entries = <1024>;
     78		bd_ram_size = <0x2000>;
     79		rx_descs = <64>;
     80		mac_control = <0x20>;
     81		slaves = <2>;
     82		active_slave = <0>;
     83		cpts_clock_mult = <0x80000000>;
     84		cpts_clock_shift = <29>;
     85		syscon = <&cm>;
     86		cpsw-phy-sel = <&phy_sel>;
     87		cpsw_emac0: slave@0 {
     88			phy_id = <&davinci_mdio>, <0>;
     89			phy-mode = "rgmii-txid";
     90			/* Filled in by U-Boot */
     91			mac-address = [ 00 00 00 00 00 00 ];
     92			phys = <&phy_gmii_sel 1 0>;
     93		};
     94		cpsw_emac1: slave@1 {
     95			phy_id = <&davinci_mdio>, <1>;
     96			phy-mode = "rgmii-txid";
     97			/* Filled in by U-Boot */
     98			mac-address = [ 00 00 00 00 00 00 ];
     99			phys = <&phy_gmii_sel 2 0>;
    100		};
    101	};
    102
    103(or)
    104	mac: ethernet@4a100000 {
    105		compatible = "ti,cpsw";
    106		ti,hwmods = "cpgmac0";
    107		cpdma_channels = <8>;
    108		ale_entries = <1024>;
    109		bd_ram_size = <0x2000>;
    110		rx_descs = <64>;
    111		mac_control = <0x20>;
    112		slaves = <2>;
    113		active_slave = <0>;
    114		cpts_clock_mult = <0x80000000>;
    115		cpts_clock_shift = <29>;
    116		syscon = <&cm>;
    117		cpsw-phy-sel = <&phy_sel>;
    118		cpsw_emac0: slave@0 {
    119			phy_id = <&davinci_mdio>, <0>;
    120			phy-mode = "rgmii-txid";
    121			/* Filled in by U-Boot */
    122			mac-address = [ 00 00 00 00 00 00 ];
    123			phys = <&phy_gmii_sel 1 0>;
    124		};
    125		cpsw_emac1: slave@1 {
    126			phy_id = <&davinci_mdio>, <1>;
    127			phy-mode = "rgmii-txid";
    128			/* Filled in by U-Boot */
    129			mac-address = [ 00 00 00 00 00 00 ];
    130			phys = <&phy_gmii_sel 2 0>;
    131		};
    132	};