realtek.yaml (13805B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/realtek.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Realtek switches for unmanaged switches 8 9allOf: 10 - $ref: dsa.yaml# 11 12maintainers: 13 - Linus Walleij <linus.walleij@linaro.org> 14 15description: 16 Realtek advertises these chips as fast/gigabit switches or unmanaged 17 switches. They can be controlled using different interfaces, like SMI, 18 MDIO or SPI. 19 20 The SMI "Simple Management Interface" is a two-wire protocol using 21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does 22 not use the MDIO protocol. This binding defines how to specify the 23 SMI-based Realtek devices. The realtek-smi driver is a platform driver 24 and it must be inserted inside a platform node. 25 26 The MDIO-connected switches use MDIO protocol to access their registers. 27 The realtek-mdio driver is an MDIO driver and it must be inserted inside 28 an MDIO node. 29 30 The compatible string is only used to identify which (silicon) family the 31 switch belongs to. Roughly speaking, a family is any set of Realtek switches 32 whose chip identification register(s) have a common location and semantics. 33 The different models in a given family can be automatically disambiguated by 34 parsing the chip identification register(s) according to the given family, 35 avoiding the need for a unique compatible string for each model. 36 37properties: 38 compatible: 39 enum: 40 - realtek,rtl8365mb 41 - realtek,rtl8366rb 42 description: | 43 realtek,rtl8365mb: 44 Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB, 45 RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S, 46 RTL8367SB, RTL8370MB, RTL8310SR 47 realtek,rtl8366rb: 48 Use with models RTL8366RB, RTL8366S 49 50 mdc-gpios: 51 description: GPIO line for the MDC clock line. 52 maxItems: 1 53 54 mdio-gpios: 55 description: GPIO line for the MDIO data line. 56 maxItems: 1 57 58 reset-gpios: 59 description: GPIO to be used to reset the whole device 60 maxItems: 1 61 62 realtek,disable-leds: 63 type: boolean 64 description: | 65 if the LED drivers are not used in the hardware design, 66 this will disable them so they are not turned on 67 and wasting power. 68 69 interrupt-controller: 70 type: object 71 description: | 72 This defines an interrupt controller with an IRQ line (typically 73 a GPIO) that will demultiplex and handle the interrupt from the single 74 interrupt line coming out of one of the Realtek switch chips. It most 75 importantly provides link up/down interrupts to the PHY blocks inside 76 the ASIC. 77 78 properties: 79 80 interrupt-controller: true 81 82 interrupts: 83 maxItems: 1 84 description: 85 A single IRQ line from the switch, either active LOW or HIGH 86 87 '#address-cells': 88 const: 0 89 90 '#interrupt-cells': 91 const: 1 92 93 required: 94 - interrupt-controller 95 - '#address-cells' 96 - '#interrupt-cells' 97 98 mdio: 99 $ref: /schemas/net/mdio.yaml# 100 unevaluatedProperties: false 101 102 properties: 103 compatible: 104 const: realtek,smi-mdio 105 106if: 107 required: 108 - reg 109 110then: 111 $ref: /schemas/spi/spi-peripheral-props.yaml# 112 not: 113 required: 114 - mdc-gpios 115 - mdio-gpios 116 - mdio 117 118 properties: 119 mdc-gpios: false 120 mdio-gpios: false 121 mdio: false 122 123else: 124 required: 125 - mdc-gpios 126 - mdio-gpios 127 - mdio 128 - reset-gpios 129 130required: 131 - compatible 132 133 # - mdc-gpios 134 # - mdio-gpios 135 # - reset-gpios 136 # - mdio 137 138unevaluatedProperties: false 139 140examples: 141 - | 142 #include <dt-bindings/gpio/gpio.h> 143 #include <dt-bindings/interrupt-controller/irq.h> 144 145 platform { 146 switch { 147 compatible = "realtek,rtl8366rb"; 148 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ 149 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; 150 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; 151 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 152 153 switch_intc1: interrupt-controller { 154 /* GPIO 15 provides the interrupt */ 155 interrupt-parent = <&gpio0>; 156 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 157 interrupt-controller; 158 #address-cells = <0>; 159 #interrupt-cells = <1>; 160 }; 161 162 ports { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 port@0 { 166 reg = <0>; 167 label = "lan0"; 168 phy-handle = <&phy0>; 169 }; 170 port@1 { 171 reg = <1>; 172 label = "lan1"; 173 phy-handle = <&phy1>; 174 }; 175 port@2 { 176 reg = <2>; 177 label = "lan2"; 178 phy-handle = <&phy2>; 179 }; 180 port@3 { 181 reg = <3>; 182 label = "lan3"; 183 phy-handle = <&phy3>; 184 }; 185 port@4 { 186 reg = <4>; 187 label = "wan"; 188 phy-handle = <&phy4>; 189 }; 190 port@5 { 191 reg = <5>; 192 label = "cpu"; 193 ethernet = <&gmac0>; 194 phy-mode = "rgmii"; 195 fixed-link { 196 speed = <1000>; 197 full-duplex; 198 }; 199 }; 200 }; 201 202 mdio { 203 compatible = "realtek,smi-mdio"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 phy0: ethernet-phy@0 { 208 reg = <0>; 209 interrupt-parent = <&switch_intc1>; 210 interrupts = <0>; 211 }; 212 phy1: ethernet-phy@1 { 213 reg = <1>; 214 interrupt-parent = <&switch_intc1>; 215 interrupts = <1>; 216 }; 217 phy2: ethernet-phy@2 { 218 reg = <2>; 219 interrupt-parent = <&switch_intc1>; 220 interrupts = <2>; 221 }; 222 phy3: ethernet-phy@3 { 223 reg = <3>; 224 interrupt-parent = <&switch_intc1>; 225 interrupts = <3>; 226 }; 227 phy4: ethernet-phy@4 { 228 reg = <4>; 229 interrupt-parent = <&switch_intc1>; 230 interrupts = <12>; 231 }; 232 }; 233 }; 234 }; 235 236 - | 237 #include <dt-bindings/gpio/gpio.h> 238 #include <dt-bindings/interrupt-controller/irq.h> 239 240 platform { 241 switch { 242 compatible = "realtek,rtl8365mb"; 243 mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; 244 mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; 245 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 246 247 switch_intc2: interrupt-controller { 248 interrupt-parent = <&gpio5>; 249 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 250 interrupt-controller; 251 #address-cells = <0>; 252 #interrupt-cells = <1>; 253 }; 254 255 ports { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 port@0 { 259 reg = <0>; 260 label = "swp0"; 261 phy-handle = <ðphy0>; 262 }; 263 port@1 { 264 reg = <1>; 265 label = "swp1"; 266 phy-handle = <ðphy1>; 267 }; 268 port@2 { 269 reg = <2>; 270 label = "swp2"; 271 phy-handle = <ðphy2>; 272 }; 273 port@3 { 274 reg = <3>; 275 label = "swp3"; 276 phy-handle = <ðphy3>; 277 }; 278 port@6 { 279 reg = <6>; 280 label = "cpu"; 281 ethernet = <&fec1>; 282 phy-mode = "rgmii"; 283 tx-internal-delay-ps = <2000>; 284 rx-internal-delay-ps = <2000>; 285 286 fixed-link { 287 speed = <1000>; 288 full-duplex; 289 pause; 290 }; 291 }; 292 }; 293 294 mdio { 295 compatible = "realtek,smi-mdio"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 ethphy0: ethernet-phy@0 { 300 reg = <0>; 301 interrupt-parent = <&switch_intc2>; 302 interrupts = <0>; 303 }; 304 ethphy1: ethernet-phy@1 { 305 reg = <1>; 306 interrupt-parent = <&switch_intc2>; 307 interrupts = <1>; 308 }; 309 ethphy2: ethernet-phy@2 { 310 reg = <2>; 311 interrupt-parent = <&switch_intc2>; 312 interrupts = <2>; 313 }; 314 ethphy3: ethernet-phy@3 { 315 reg = <3>; 316 interrupt-parent = <&switch_intc2>; 317 interrupts = <3>; 318 }; 319 }; 320 }; 321 }; 322 323 - | 324 #include <dt-bindings/gpio/gpio.h> 325 #include <dt-bindings/interrupt-controller/irq.h> 326 327 mdio { 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 switch@29 { 332 compatible = "realtek,rtl8365mb"; 333 reg = <29>; 334 335 reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; 336 337 switch_intc3: interrupt-controller { 338 interrupt-parent = <&gpio0>; 339 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 340 interrupt-controller; 341 #address-cells = <0>; 342 #interrupt-cells = <1>; 343 }; 344 345 ports { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 349 port@0 { 350 reg = <0>; 351 label = "lan4"; 352 }; 353 354 port@1 { 355 reg = <1>; 356 label = "lan3"; 357 }; 358 359 port@2 { 360 reg = <2>; 361 label = "lan2"; 362 }; 363 364 port@3 { 365 reg = <3>; 366 label = "lan1"; 367 }; 368 369 port@4 { 370 reg = <4>; 371 label = "wan"; 372 }; 373 374 port@7 { 375 reg = <7>; 376 ethernet = <ðernet>; 377 phy-mode = "rgmii"; 378 tx-internal-delay-ps = <2000>; 379 rx-internal-delay-ps = <0>; 380 381 fixed-link { 382 speed = <1000>; 383 full-duplex; 384 }; 385 }; 386 }; 387 }; 388 };