fsl,fec.yaml (6988B)
1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/fsl,fec.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Fast Ethernet Controller (FEC) 8 9maintainers: 10 - Joakim Zhang <qiangqing.zhang@nxp.com> 11 12allOf: 13 - $ref: ethernet-controller.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - enum: 19 - fsl,imx25-fec 20 - fsl,imx27-fec 21 - fsl,imx28-fec 22 - fsl,imx6q-fec 23 - fsl,mvf600-fec 24 - items: 25 - enum: 26 - fsl,imx53-fec 27 - fsl,imx6sl-fec 28 - const: fsl,imx25-fec 29 - items: 30 - enum: 31 - fsl,imx35-fec 32 - fsl,imx51-fec 33 - const: fsl,imx27-fec 34 - items: 35 - enum: 36 - fsl,imx6ul-fec 37 - fsl,imx6sx-fec 38 - const: fsl,imx6q-fec 39 - items: 40 - enum: 41 - fsl,imx7d-fec 42 - const: fsl,imx6sx-fec 43 - items: 44 - const: fsl,imx8mq-fec 45 - const: fsl,imx6sx-fec 46 - items: 47 - enum: 48 - fsl,imx8mm-fec 49 - fsl,imx8mn-fec 50 - fsl,imx8mp-fec 51 - const: fsl,imx8mq-fec 52 - const: fsl,imx6sx-fec 53 - items: 54 - const: fsl,imx8qm-fec 55 - const: fsl,imx6sx-fec 56 - items: 57 - enum: 58 - fsl,imx8qxp-fec 59 - const: fsl,imx8qm-fec 60 - const: fsl,imx6sx-fec 61 62 reg: 63 maxItems: 1 64 65 interrupts: 66 minItems: 1 67 maxItems: 4 68 69 interrupt-names: 70 oneOf: 71 - items: 72 - const: int0 73 - items: 74 - const: int0 75 - const: pps 76 - items: 77 - const: int0 78 - const: int1 79 - const: int2 80 - items: 81 - const: int0 82 - const: int1 83 - const: int2 84 - const: pps 85 86 clocks: 87 minItems: 2 88 maxItems: 5 89 description: 90 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. 91 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. 92 The "ptp"(option), for IEEE1588 timer clock that requires the clock. 93 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like 94 RGMII TXC clock or RMII reference clock. It depends on board design, 95 the clock is required if RGMII TXC and RMII reference clock source from 96 SOC internal PLL. 97 The "enet_out"(option), output clock for external device, like supply clock 98 for PHY. The clock is required if PHY clock source from SOC. 99 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz. 100 The clock is required if SoC RGMII enable clock delay. 101 102 clock-names: 103 minItems: 2 104 maxItems: 5 105 items: 106 enum: 107 - ipg 108 - ahb 109 - ptp 110 - enet_clk_ref 111 - enet_out 112 - enet_2x_txclk 113 114 phy-mode: true 115 116 phy-handle: true 117 118 fixed-link: true 119 120 local-mac-address: true 121 122 mac-address: true 123 124 tx-internal-delay-ps: 125 enum: [0, 2000] 126 127 rx-internal-delay-ps: 128 enum: [0, 2000] 129 130 phy-supply: 131 description: 132 Regulator that powers the Ethernet PHY. 133 134 fsl,num-tx-queues: 135 $ref: /schemas/types.yaml#/definitions/uint32 136 description: 137 The property is valid for enet-avb IP, which supports hw multi queues. 138 Should specify the tx queue number, otherwise set tx queue number to 1. 139 enum: [1, 2, 3] 140 141 fsl,num-rx-queues: 142 $ref: /schemas/types.yaml#/definitions/uint32 143 description: 144 The property is valid for enet-avb IP, which supports hw multi queues. 145 Should specify the rx queue number, otherwise set rx queue number to 1. 146 enum: [1, 2, 3] 147 148 fsl,magic-packet: 149 $ref: /schemas/types.yaml#/definitions/flag 150 description: 151 If present, indicates that the hardware supports waking up via magic packet. 152 153 fsl,err006687-workaround-present: 154 $ref: /schemas/types.yaml#/definitions/flag 155 description: 156 If present indicates that the system has the hardware workaround for 157 ERR006687 applied and does not need a software workaround. 158 159 fsl,stop-mode: 160 $ref: /schemas/types.yaml#/definitions/phandle-array 161 items: 162 - items: 163 - description: phandle to general purpose register node 164 - description: the gpr register offset for ENET stop request 165 - description: the gpr bit offset for ENET stop request 166 description: 167 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. 168 169 mdio: 170 $ref: mdio.yaml# 171 unevaluatedProperties: false 172 description: 173 Specifies the mdio bus in the FEC, used as a container for phy nodes. 174 175 # Deprecated optional properties: 176 # To avoid these, create a phy node according to ethernet-phy.yaml in the same 177 # directory, and point the FEC's "phy-handle" property to it. Then use 178 # the phy's reset binding, again described by ethernet-phy.yaml. 179 180 phy-reset-gpios: 181 deprecated: true 182 description: 183 Should specify the gpio for phy reset. 184 185 phy-reset-duration: 186 deprecated: true 187 description: 188 Reset duration in milliseconds. Should present only if property 189 "phy-reset-gpios" is available. Missing the property will have the 190 duration be 1 millisecond. Numbers greater than 1000 are invalid 191 and 1 millisecond will be used instead. 192 193 phy-reset-active-high: 194 deprecated: true 195 description: 196 If present then the reset sequence using the GPIO specified in the 197 "phy-reset-gpios" property is reversed (H=reset state, L=operation state). 198 199 phy-reset-post-delay: 200 deprecated: true 201 description: 202 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay 203 milliseconds will be observed after the phy-reset-gpios has been toggled. 204 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. 205 Other delays are invalid. 206 207required: 208 - compatible 209 - reg 210 - interrupts 211 212# FIXME: We had better set additionalProperties to false to avoid invalid or at 213# least undocumented properties. However, PHY may have a deprecated option to 214# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find 215# these boards which is based on i.MX6QDL. 216additionalProperties: false 217 218examples: 219 - | 220 ethernet@83fec000 { 221 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 222 reg = <0x83fec000 0x4000>; 223 interrupts = <87>; 224 phy-mode = "mii"; 225 phy-reset-gpios = <&gpio2 14 0>; 226 phy-supply = <®_fec_supply>; 227 }; 228 229 ethernet@83fed000 { 230 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 231 reg = <0x83fed000 0x4000>; 232 interrupts = <87>; 233 phy-mode = "mii"; 234 phy-reset-gpios = <&gpio2 14 0>; 235 phy-supply = <®_fec_supply>; 236 phy-handle = <ðphy0>; 237 238 mdio { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 242 ethphy0: ethernet-phy@0 { 243 compatible = "ethernet-phy-ieee802.3-c22"; 244 reg = <0>; 245 }; 246 }; 247 };