cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell,mvusb.yaml (1732B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/net/marvell,mvusb.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Marvell USB to MDIO Controller
      8
      9maintainers:
     10  - Tobias Waldekranz <tobias@waldekranz.com>
     11
     12description: |+
     13  This controller is mounted on development boards for Marvell's Link Street
     14  family of Ethernet switches. It allows you to configure the switch's registers
     15  using the standard MDIO interface.
     16
     17  Since the device is connected over USB, there is no strict requirement of
     18  having a device tree representation of the device. But in order to use it with
     19  the mv88e6xxx driver, you need a device tree node in which to place the switch
     20  definition.
     21
     22allOf:
     23  - $ref: "mdio.yaml#"
     24
     25properties:
     26  compatible:
     27    const: usb1286,1fa4
     28  reg:
     29    maxItems: 1
     30    description: The USB port number on the host controller
     31
     32required:
     33  - compatible
     34  - reg
     35  - "#address-cells"
     36  - "#size-cells"
     37
     38unevaluatedProperties: false
     39
     40examples:
     41  - |
     42    /* USB host controller */
     43    usb {
     44            #address-cells = <1>;
     45            #size-cells = <0>;
     46
     47            mdio@1 {
     48                    compatible = "usb1286,1fa4";
     49                    reg = <1>;
     50                    #address-cells = <1>;
     51                    #size-cells = <0>;
     52
     53                    switch@0 {
     54                            compatible = "marvell,mv88e6190";
     55                            reg = <0x0>;
     56
     57                            ports {
     58                                    /* Port definitions */
     59                            };
     60
     61                            mdio {
     62                                    /* PHY definitions */
     63                            };
     64                    };
     65            };
     66    };